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X1203S8I PDF预览

X1203S8I

更新时间: 2024-10-02 23:29:31
品牌 Logo 应用领域
其他 - ETC 外围集成电路光电二极管时钟
页数 文件大小 规格书
19页 157K
描述
Real-Time Clock

X1203S8I 数据手册

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2-WireRTC  
X1203  
Real Time Clock/Calendar/Alarm  
DESCRIPTION  
FEATURES  
• 2 alarms—interrupt output  
—Settable on the second, minute, hour, day,  
month, or day of the week  
—Repeat alarm for time base generation  
• 2-wire interface interoperable with I2C  
—400kHz data transfer rate  
• Secondary power supply input with internal  
switch-over circuitry  
• Low power CMOS  
—<1µA operating current  
—<3mA active current during program  
—<400µA active current during data read  
• Typical nonvolatile write cycle time: 5ms  
• High reliability  
The X1203 is a Real Time Clock with clock/calendar  
circuits and two alarms. The dual port clock and alarm  
registers allow the clock to operate, without loss of  
accuracy, even during read and write operations.  
The clock/calendar provides functionality that is con-  
trollable and readable through a set of registers. The  
clock, using a low cost 32.768kHz crystal input, accu-  
rately tracks the time in seconds, minutes, hours, date,  
day, month and years. It has leap year correction,  
automatic adjustment for the year 2000 and months  
with less than 31 days.  
An alarm match of the RTC sets an interrupt flag and  
activates an interrupt pin. An alternative alarm function  
provides a pulsed interrupt for long time constant time-  
bases.  
• Small package options  
—8-lead SOIC package, 8-lead TSSOP package  
The device offers a backup power input pin. This  
V
pin allows the device to be backed up by a non-  
BACK  
rechargeable battery. The RTC is fully operational from  
2.7 to 5.5 Volts and the RTC portion of the X1203  
device remains fully operational down to 1.8 Volts.  
BLOCK DIAGRAM  
X1  
Timer  
Calendar  
Logic  
Frequency  
Divider  
1Hz  
32.768kHz  
Oscillator  
Time  
X2  
Keeping  
Registers  
(SRAM)  
Control  
Status  
Control  
Decode  
Logic  
Compare  
Registers  
Registers  
Alarm  
(EEPROM)  
(SRAM)  
Serial  
Interface  
Decoder  
SCL  
SDA  
Alarm Regs  
(EEPROM)  
8
Interrupt Enable  
Alarm  
IRQ  
Characteristics subject to change without notice. 1 of 19  
REV 1.2.0 2/13/01 James Tsang  
www.xicor.com  

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