Datasheet > W3EG7265S262JD3F

W3EG7265S262JD3F

更新时间： 2024-01-19 00:25:10

品牌	Logo	应用领域
WEDC		动态存储器
页数	文件大小	规格书
12页	194K
描述
DRAM,

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中文翻译

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技术参数
数据手册

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W3EG7265S262JD3F 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.68
Base Number Matches：	1

W3EG7265S262JD3F 数据手册

W3EG7265S-JD3

White Electronic Designs

PRELIMINARY*

512MB – 2x32Mx72 DDR SDRAM REGISTERED, w/PLL

FEATURES

DESCRIPTION

ꢀ

Double-data-rate architecture

The W3EG7265S is a 2x32Mx72 Double Data Rate

SDRAM memory module based on 256Mb DDR

SDRAM components. The module consists of eighteen

32Mx8 DDR SDRAMs in 66 pin TSOP package

mounted on a 184 Pin FR4 substrate.

ꢀ

DDR200 and DDR266

• JEDEC design speciﬁcaitons

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2,5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

ꢀ

Synchronous design allows precise cycle control with

the use of system clock. Data I/O transactions are

possible on both edges and Burst Lenths allow the

same device to be useful for a variety of high bandwidth,

high performance memory system applications.

Serial presence detect

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

Power Supply: 2.5V 0.2V

JEDEC standard 184 pin DIMM package

• PCB height: 30.48mm (1.20")

NOTE: Consult factory for availability of:

• Lead-free products

• Vendor source control option

• Industrial temperature option

OPERATING FREQUENCIES

DDR266 @CL=2

133MHz

DDR266 @CL=2.5

133MHz

DDR200 @CL=2

100MHz

Clock Speed

CL-t_RCD-t_RP

2-2-2

2.5-3-3

2-2-2

January 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...12

中文翻译

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