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W3EG7218S202AD4

更新时间： 2024-09-30 04:25:43

品牌	Logo	应用领域
WEDC		存储内存集成电路动态存储器双倍数据速率
页数	文件大小	规格书
13页	165K
描述
128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL

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W3EG7218S202AD4 数据手册

W3EG7218S-AD4

-BD4

White Electronic Designs

PRELIMINARY*

128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLL

FEATURES

DESCRIPTION

ꢀ

Double-data-rate architecture

The W3EG7218S is a 16Mx72 Double Data Rate

SDRAM memory module based on 128Mb DDR

SDRAM component. The module consists of nine

16Mx8 DDR SDRAMs in 66 pin TSOP package

mounted on a 200 Pin FR4 substrate.

DDR200 and DDR266

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2,5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

Synchronous design allows precise cycle control with

the use of system clock. Data I/O transactions are

possible on both edges and Burst Lenths allow the

same device to be useful for a variety of high bandwidth,

high performance memory system applications.

Serial presence detect

Power Supply: 2.5V 0.20V

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

JEDEC standard 200 pin SO-DIMM package

•

Package height options:

AD4: 35.5mm (1.38") and

BD4: 31.75mm (1.25")

OPERATING FREQUENCIES

DDR266 @CL=2

133MHz

DDR266 @CL=2.5

133MHz

DDR200 @CL=2

100MHz

Clock Speed

CL-t_RCD-t_RP

2-2-2

2.5-3-3

2-2-2

November 2004

Rev. 1

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...13

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