W3EG6418S-D3
-JD3
White Electronic Designs
PRELIMINARY*
128MB – 16Mx64 DDR SDRAM UNBUFFERED
FEATURES
DESCRIPTION
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Double-data-rate architecture
The W3DG6418S is a 16Mx64 Double Data Rate
SDRAM memory module based on 128Mb DDR SDRAM
components. The module consists of eight 16Mx8 DDR
SDRAMs in 66 pin TSOP package mounted on a 184
Pin FR4 substrate.
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DDR200 and DDR266
• JEDEC design specifications
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Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
* This product is under development, is not qualified or characterized and is subject
to change without notice.
Serial presence detect
Power Supply: 2.5V 0.20V
JEDEC standard 184 pin DIMM package
• JD3 PCB height: 30.48mm (1.20") MAX
NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
DDR266 @CL=2
133MHz
DDR266 @CL=2.5
133MHz
DDR200 @CL=2
100MHz
Clock Speed
CL-tRCD-tRP
2-2-2
2-3-3
2.5-3-3
2-2-2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com