Datasheet > W134HT

W134HT

更新时间： 2024-01-21 03:08:07

品牌	Logo	应用领域
芯科 - SILICON		光电二极管外围集成电路
页数	文件大小	规格书
11页	112K
描述
Direct Rambusâ¢ Clock Generator

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技术参数
数据手册

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W134HT 技术参数

生命周期：	Transferred	零件包装代码：	SOIC
包装说明：	,	针数：	24
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.48
JESD-30 代码：	R-PDSO-G24	端子数量：	24
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
表面贴装：	YES	技术：	CMOS
端子形式：	GULL WING	端子位置：	DUAL
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

W134HT 数据手册

W134

Table 8. State Transition Latency Specifications (continued)

Transition Latency

Transition

From

Parameter

Max.

Description

Clk Stop

Normal

t_CLKON

10 ns Time from StopB until Clk/ClkB provides glitch-free

clock edges.

Clk Stop

Normal

t_CLKSETL20 cycles Time from StopB to Clk/ClkB output settled to within 50

ps of the phase before CLK/CLKB was disabled.

Normal

Test

Clk Stop

Normal

t_CLKOFF

t_CTL

5 ns

Time from StopB to Clk/ClkB output disabled.

3 ms

Time from when S0 or S1 is changed until CLK/CLKB

output has resettled (excluding t_DISTLOCK).

Normal

Test

t_CTL

3 ms

1 ms

Time from when S0 or S1 is changed until CLK/CLKB

output has resettled (excluding t_DISTLOCK).

B,D

Normal or Clk Stop Power-down t_POWERDN

Time from PwrDnB to the device in Power-down.

Figure 5 shows that the Clk Stop to Normal transition goes

through three phases. During t_CLKON, the clock output is not

specified and can have glitches. For t_CLKON< t < t_CLKSETL, the

clock output is enabled and must be glitch-free. For

t > t_CLKSETL, the clock output phase must be settled to within

50 ps of the phase before the clock output was disabled. At

this time, the clock output must also meet the voltage and

timing specifications of the Device Characteristics table. The

outputs are in a high-impedance state during the Clk Stop

mode.

Table 9. Distributed Loop Lock Time Specification

Parameter

Description

Min.

Max.

Unit

t_DISTLOCKTime from when Clk/ClkB output is settled to when the phase error between SynclkN and

PclkM falls within the t_ERR,PDspec in Table .

Table 10.Supply and Reference Current Specification

Parameter

I_POWERDOWN

I_CLKSTOP

Description

Min.

Max.

250

Unit

µA

“Supply” current in Power-down state (PwrDnB 1 = 0)

–

“Supply” current in Clk Stop state (StopB = 0)

µA

I_NORMAL

“Supply” current in Normal state (StopB = 1, PwrDnB = 1)

Current at VDDIR or VDDIPD reference pin in Power-down state (PwrDnB = 0)

Current at VDDIR or VDDIPD reference pin in Normal or Clk Stop state (PwrDnB = 1)

100

I_REF,PWDN

I_REF,NORM

........................Document #: 38-07426 Rev. *C Page 7 of 11

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