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W134HT

更新时间： 2024-01-25 22:43:36
品牌 Logo 应用领域
芯科 - SILICON 光电二极管外围集成电路
页数 文件大小 规格书
11页 112K
描述
Direct Rambus™ Clock Generator

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W134HT 技术参数

生命周期：Transferred零件包装代码：SOIC
包装说明：,针数：24
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.48
JESD-30 代码：R-PDSO-G24端子数量：24
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
表面贴装：YES技术：CMOS
端子形式：GULL WING端子位置：DUAL
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

W134HT 数据手册

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W134  
and S1 must be stable before power is applied to the device,  
and can only be changed in Power-down mode (PwrDnB = 0).  
The reference inputs, VDDR and VDDPD, may remain on or may  
be grounded during the Power-down mode.  
Table 4. Bypass and Test Mode Selection  
Bypclk  
Mode  
S0  
S1  
(int.)  
Gnd  
–
Clk  
PAclk  
Hi-Z  
ClkB  
PAclkB  
Hi-Z  
Normal  
0
0
Table 6. Examples of Frequencies, Dividers, and Gear Ratios  
Pclk Refclk Busclk Synclk A B M N Ratio F@PD  
Output Test (OE)  
Bypass  
0
1
1
0
PLLclk PLLclk PLLclkB  
Refclk Refclk RefclkB  
67  
33  
50  
50  
67  
67  
267  
300  
400  
267  
400  
67  
75  
8 1 2 2 1.0  
6 1 8 6 1.33  
8 1 4 4 1.0  
4 1 4 2 2.0  
6 1 8 6 1.33  
33  
12.5  
25  
Test  
1
1
100  
100  
133  
133  
100  
67  
Table 5 shows the logic for selecting the Power-down mode,  
using the PwrDnB input signal. PwrDnB is active LOW  
(enabled when 0). When PwrDnB is disabled, the DRCG is in  
its normal mode. When PwrDnB is enabled, the DRCG is put  
into a powered-off state, and the Clk and ClkB outputs are  
three-stated.  
33  
100  
16.7  
The control signals Mult0 and Mult1 can be used in two ways.  
If they are changed during Power-down mode, then the  
Power-down transition timings determine the settling time of  
the DRCG. However, the Mult0 and Mult1 control signals can  
also be changed during Normal mode. When the Mult control  
signals are “hot-swapped” in this manner, the Mult transition  
timings determine the settling time of the DRCG.  
Table 5. Power-down Mode Selection  
Mode  
Normal  
PwrDnB  
Clk  
ClkB  
PAclkB  
GND  
1
0
PAclk  
GND  
Power-down  
In Normal mode, the clock source is on, and the output is  
enabled.  
Table of Frequencies and Gear Ratios  
Table 6 shows several supported Pclk and Busclk  
frequencies, the corresponding A and B dividers required in  
the DRCG PLL, and the corresponding M and N dividers in the  
gear ratio logic. The column Ratio gives the Gear Ratio as  
defined Pclk/Synclk (same as M and N). The column F@PD  
gives the divided down frequency (in MHz) at the Phase  
Detector, where F@PD = Pclk/M = Synclk/N.  
Table 7 lists the control signals for each state.  
Table 7. Control Signals for Clock Source States  
Clock  
Output  
Buffer  
State  
Power-down  
Clock Stop  
Normal  
PwrDnB  
StopB  
Source  
0
1
1
X
0
1
OFF  
ON  
Ground  
Disabled  
Enabled  
State Transitions  
ON  
The clock source has three fundamental operating states.  
Figure 4 shows the state diagram with each transition labelled  
A through H. Note that the clock source output may NOT be  
glitch-free during state transitions.  
Figure 5 shows the timing diagrams for the various transitions  
between states, and Table 8 specifies the latencies of each  
state transition. Note that these transition latencies assume  
the following.  
Upon powering up the device, the device can enter any state,  
depending on the settings of the control signals, PwrDnB and  
StopB.  
Refclk input has settled and meets specification shown in the  
Operating Conditions table.  
The Mult0, Mult1, S0 and S1 control signals are stable.  
In Power-down mode, the clock source is powered down with  
the control signal, PwrDnB, equal to 0. The control signals S0  
VDD Turn-On  
M
VDD Turn-On  
G
J
L
Test  
Normal  
N
B
F
K
A
E
VDD Turn-On  
H
VDD Turn-On  
D
C
Power-Down  
Clk Stop  
Figure 4. Clock Source State Diagram  
........................Document #: 38-07426 Rev. *C Page 5 of 11  
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