Datasheet > W134H

W134H

更新时间： 2024-02-18 06:07:04

品牌	Logo	应用领域
芯科 - SILICON		光电二极管
页数	文件大小	规格书
11页	112K
描述
Direct Rambusâ¢ Clock Generator

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技术参数
数据手册

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W134H 技术参数

生命周期：	Transferred	零件包装代码：	SOIC
包装说明：	,	针数：	24
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.48
JESD-30 代码：	R-PDSO-G24	端子数量：	24
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
表面贴装：	YES	技术：	CMOS
端子形式：	GULL WING	端子位置：	DUAL
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

W134H 数据手册

W134

Pin Definitions

Pin Name

No.

Type

Description

REFCLK

Reference Clock Input. Reference clock input, normally supplied by a system frequency

synthesizer (Cypress W133).

PCLKM

Phase Detector Input. The phase difference between this signal and SYNCLKN is used

to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and

SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio

Logic is not used, this pin would be connected to Ground.

SYNCLKN

Phase Detector Input. The phase difference between this signal and PCLKM is used to

synchronize the Rambus Channel Clock with the system clock. Both PCLKM and

SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio

Logic is not used, this pin would be connected to Ground.

STOPB

Clock Output Enable. When this input is driven to active LOW, it disables the differential

Rambus Channel clocks.

PWRDNB

MULT 0:1

Active LOW Power-down. When this input is driven to active LOW, it disables the differ-

ential Rambus Channel clocks and places the W134M/W134S in power-down mode.

15, 14

PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to

determine the multiply ratio for the PLL for the input REFCLK.

W134S

W134M

PLL/REFCLK

MULT0

MULT1

4.5

5.333

CLK, CLKB

S0, S1

20, 18

24, 23

Complementary Output Clock. Differential Rambus Channel clock outputs.

Mode Control Input. These inputs control the operating mode of the W134M/W134S.

MODE

Normal

Output Enable Test

Bypass

Test

–

No Connect

VDDIR

VDDIPD

RefV Reference for REFCLK. Voltage reference for input reference clock.

RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB.

VDD

3, 9, 16, 22

Power Connection. Power supply for core logic and output buffers. Connected to 3.3V

supply.

GND

4, 5, 8, 13, 17,

Ground Connection. Connect all ground pins to the common system ground plane.

W134M/W134S

W133

W158

W159

W161

W167

Refclk

Phase

PLL

Busclk

Align

CY2210

RAC

RMC

Pclk

DLL

Synclk

Gear

Ratio

Logic

Figure 1. DDLL System Architecture

........................Document #: 38-07426 Rev. *C Page 2 of 11

123 4 5 6 7...11

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