VSC8502
Dual Port GbE Copper PHY with Synchronous Ethernet and RGMII/GMII Interface
Low-power PHY supports IEEE 802.3az Energy Efficient Ethernet.
Highlights
• EcoEthernet™ 2.0, the gold standard for
Energy Efficient Ethernet (EEE)
The VSC8502 device is designed for space-constrained
10/100/1000BASE-T applications. It features integrated line-side
termination to conserve board space, to lower EMI, and to improve
system performance. To further reduce system complexity, component
count, and system cost, the VSC8502 device can operate from a
single 3.3 V supply using integrated voltage regulators that provide the
necessary 1.0 V and 2.5 V rails for operation. Additionally, integrated
RGMII timing compensation eliminates the need for on-board delay
lines.
• Wake-on-LAN (WOL)
• Fast link failure indication
• Synchronous Ethernet support
• Dual recovered clocks for timing reference
• Ring Resiliency™
• Integrated voltage regulator
• Pin compatible with VSC8501
The VSC8502 device includes Microsemi’s EcoEthernet™ 2.0
technology that supports Energy Efficient Ethernet and power saving
features to reduce power based on link state and cable reach. The
device optimizes power consumption in all link operating speeds and
features Wake-on-LAN (WOL) power management using magic packets.
Applications
• IoT applications such as digital signage,
eHealth, and industrial grade switches
• Consumer electronics such as CPE,
UHDTV, media servers, and NAS
The VSC8502 device also includes fast link failure indication for high-
availability networks. Fast link failure indication identifies the onset of
a link failure in less than 1 ms typical to go beyond the IEEE 802.3
standard requirement of 750 ms 10 ms (link master).
• Wireless backhaul
• Small cells, femtocells
Synchronous Ethernet and Ring Resiliency™ are supported. The device
has two recovered clock outputs for Synchronous Ethernet applications.
Programmable clock squelch control is included to inhibit undesirable
clocks from propagating and to help prevent timing loops. Ring
Resiliency allows a PHY port to switch between master and slave timing
references with no link drop in 1000BASE-T mode.
3.3 V
10/100/1000BASE-T MAC,
Switching ASIC,
or Network Processor
VSC8502
Dual Port
PHY
RGMII/GMII
RJ45+Magnetics
25 MHz
Management I/F (MDC / MDIO)
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability
whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction
with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone
and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability
of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer.
Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in
this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.
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