Datasheet > VSC852TP

VSC852TP

更新时间： 2024-02-07 08:34:42

品牌	Logo	应用领域
VITESSE		电信电信集成电路
页数	文件大小	规格书
16页	643K
描述
Digital Time Switch, PBGA440, 35 X 35 MM, BGA-440

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VSC852TP 技术参数

生命周期：	Contact Manufacturer	包装说明：	BGA,
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.81	JESD-30 代码：	S-PBGA-B440
长度：	35 mm	功能数量：	1
端子数量：	440	最高工作温度：	85 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	认证状态：	Not Qualified
座面最大高度：	2.65 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	DIGITAL TIME SWITCH
温度等级：	OTHER	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
宽度：	35 mm	Base Number Matches：	1

VSC852TP 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

1.6Gb/s 64x64

Crosspoint Switch

VSC852

Features

• 64 Input by 64 Output Non-Blocking

• Fully Differential Data Path, PECL-Compatible

• Full Broadcast/Multicast Capability

• 1.6Gb/s NRZ Data Bandwidth

• Designed for HDTV, GE, and FC

• TTL-Compatible Control I/O

• On-Chip Input Terminations

• Single 3.3V Supply, 28W Maximum Dissipation

• High Performance 35mm, 440 BGA Package

General Description

The VSC852 is a monolithic 64x64 asynchronous crosspoint switch, designed to carry broadband data

streams up to 1.6Gb/s. Typical applications include Gigabit Fibre Channel/Ethernet and HDTV. The non-

blocking switch core is programmed through a serial port interface that allows random access programming of

each output port. A high degree of signal integrity is maintained throughout the chip via fully differential signal

paths.

The crosspoint function is based on a multiplexer tree architecture. Each data output is driven by a 64:1

multiplexer tree that can be programmed to one and only one of its 64 inputs. The signal path is unregistered, so

no clock is required for the data inputs. The signal path is asynchronous, so there are no restrictions on the

phase, frequency, or signal pattern at each input. (Note: the maximum frequency for any data line is 1.6Gb/s.)

Each output driver is a fully differential switched current driver with on-die back-terminations for maxi-

mum signal integrity. Data inputs are terminated on die through 50W resistors to an external V supply.

The serial port interface uses TTL levels and provides separate pins for data input and output. Core pro-

gramming can be sequential for each address or multiple program assignments can be queued and issued simul-

taneously.

VSC852 Block Diagram

G52245-0, Rev 4.1

9/26/00

Page 1

Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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