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VN10KN3-P002-G PDF预览

VN10KN3-P002-G

更新时间: 2024-10-01 12:03:15
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
6页 631K
描述
N-Channel Enhancement-Mode Vertical DMOS FET

VN10KN3-P002-G 数据手册

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Supertex inc.  
VN10K  
N-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
This enhancement-mode (normally-off) transistor utilizes a  
vertical DMOS structure and Supertex’s well-proven, silicon-  
gate manufacturing process. This combination produces a  
devicewiththepowerhandlingcapabilitiesofbipolartransistors  
and the high input impedance and positive temperature  
coefficient inherent in MOS devices. Characteristic of all  
MOS structures, this device is free from thermal runaway and  
thermally-induced secondary breakdown.  
Free from secondary breakdown  
Low power drive requirement  
Ease of paralleling  
Low CISS and fast switching speeds  
Excellent thermal stability  
Integral source-drain diode  
High input impedance and high gain  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching speeds  
are desired.  
Applications  
Motor controls  
Converters  
Amplifiers  
Switches  
Power supply circuits  
Drivers (relays, hammers, solenoids, lamps,  
memories, displays, bipolar transistors, etc.)  
Ordering Information  
RDS(ON)  
ID(ON)  
Package  
Device  
TO-92  
BVDSS/BVDGS  
(max)  
(Ω)  
(min)  
(mA)  
(V)  
VN10K  
VN10KN3-G  
60  
5.0  
750  
For packaged products, -G indicates package is RoHS compliant (‘Green’).  
Consult factory for die / wafer form part numbers.  
Refer to Die Specification VF21 for layout and dimensions.  
Absolute Maximum Ratings  
Pin Configuration  
Parameter  
Value  
BVDSS  
BVDGS  
±30V  
Drain-to-source voltage  
Drain-to-gate voltage  
Gate-to-source voltage  
DRAIN  
SOURCE  
Operating and storage temperature  
-55OC to +150OC  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
GATE  
TO-92 (N3)  
Product Marking  
SiVN  
1 0 K  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
= “Green” Packaging  
Package may or may not include the following marks: Si or  
TO-92 (N3)  
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com  

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N-Channel Enhancement-Mode Vertical DMOS FET