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VFC320BM2 PDF预览

VFC320BM2

更新时间： 2024-02-02 16:33:01
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
12页 234K
描述
Voltage-to-Frequency and Frequency-to-Voltage CONVERTER

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VFC320BM2 技术参数

是否无铅： 含铅生命周期：Obsolete
零件包装代码：SMT包装说明：,
针数：10Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.67转换器类型：VOLTAGE TO FREQUENCY CONVERTER
JESD-30 代码：O-MBCY-W10最大线性误差 (EL)：0.03%
最大负电源电压：-20 V最小负电源电压：-13 V
标称负供电电压：-15 V功能数量：1
端子数量：10最大工作频率：1 MHz
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：METAL封装形状：ROUND
封装形式：CYLINDRICAL认证状态：Not Qualified
最大供电电压：20 V最小供电电压：13 V
标称供电电压：15 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子形式：WIRE端子位置：BOTTOM
Base Number Matches：1

VFC320BM2 数据手册

 浏览型号VFC320BM2的Datasheet PDF文件第1页浏览型号VFC320BM2的Datasheet PDF文件第3页浏览型号VFC320BM2的Datasheet PDF文件第4页浏览型号VFC320BM2的Datasheet PDF文件第5页浏览型号VFC320BM2的Datasheet PDF文件第6页浏览型号VFC320BM2的Datasheet PDF文件第7页 
ELECTRICAL CHARACTERISTICS  
At TA = +25°C and ±15VDC power supply, unless otherwise noted.  
VFC320BP  
TYP  
VFC320CP  
TYP  
PARAMETER  
CONDITIONS  
MIN  
MAX  
MIN  
MAX  
UNITS  
V/F CONVERTER fOUT = VIN/7.5 R1C1, Figure 4  
INPUT TO OP AMP  
Voltage Range(1)  
Fig. 4 with e2 = 0  
Fig. 4 with e1 = 0  
IIN = VIN/RIN  
>0  
<0  
+0.25  
Note 2  
–10  
+750  
V
V
µA  
Current Range(1)  
Bias Current  
ꢀ
ꢀ
Inverting Input  
4
10  
8
30  
±0.15  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
nA  
nA  
mV  
µV/°C  
kΩ || pF  
Noninverting Input  
Offset Voltage(3)  
Offset Voltage Drift  
Differential Impedance  
Common-Mode  
Impedance  
±5  
ꢀ
ꢀ
300 || 5 650 || 5  
ꢀ
ꢀ
300 || 3 500 || 3  
ꢀ
kΩ || pF  
ACCURACY  
Linearity Error(1) (4) (5)  
Fig. 4 with e2 = 0(6)  
0.01Hz ≤ fOUT ≤ 10kHz  
0.1Hz ≤ fOUT ≤ 100kHz  
1Hz ≤ fOUT ≤ 1MHz  
±0.004  
±0.008  
±0.1  
±0.005  
±0.030  
±0.0015  
±0.002  
ꢀ
% FSR  
% FSR  
% FSR  
ꢀ
ꢀ
Offset Error Input  
Offset Voltage(3)  
±15  
ꢀ
ppm FSR  
ppm FSR/°C  
% FSR  
ppm FSR/°C  
ppm FSR/°C  
Offset Drift(7)  
±0.5  
±5  
ꢀ
ꢀ
Gain Error(3)  
Gain Drift(7)  
Full Scale Drift  
±10  
50  
50  
ꢀ
20  
20  
f = 10kHz  
f = 10kHz  
(Offset Drift and Gain Drift)(7)(8)(9)  
Power Supply Sensitivity  
±VCC = 14VDC to 18VDC  
CLOAD ≤ 50pF  
±0.015  
ꢀ
ꢀ
% FSR%  
DYNAMIC RESPONSE  
Full Scale Frequency  
Dynamic Range  
1
MHz  
Decades  
6
ꢀ
Settling Time  
(V/F) to Specified Linearity  
For a Full Scale Input Step  
<50% Overload  
Note 10  
Note 10  
ꢀ
ꢀ
Overload Recovery  
OPEN COLLECTOR OUTPUT  
Voltage, Logic “0”  
Leakage Current, Logic “1”  
Voltage, Logic “1”  
I
SINK = 8mA, max  
0.4  
1.0  
ꢀ
ꢀ
V
µA  
V
O = 15V  
0.01  
ꢀ
External Pull-up Resistor  
Required (See Figure 4)  
For Best Linearity  
VPU  
ꢀ
V
%
ns  
Duty Cycle at FS  
Fall Time  
25  
100  
ꢀ
ꢀ
IOUT = 5mA, CLOAD = 500pF  
F/V CONVERTER VOUT = 7.5 R1C1 fIN, Figure 9  
INPUT TO COMPARATOR  
Impedance  
Logic “1”  
Logic “0”  
Pulse-width Range  
50 || 10 150 || 10  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
kΩ || pF  
+1.0  
–VCC  
0.25  
+VCC  
–0.05  
ꢀ
ꢀ
V
V
µs  
OUTPUT FROM OP AMP  
Voltage  
Current  
Impedance  
Capacitive Load  
I
V
O = 6mA  
O = 7VDC  
Closed-Loop  
Without Oscillation  
0 to +10  
+10  
ꢀ
ꢀ
V
mA  
Ω
0.1  
100  
ꢀ
ꢀ
pF  
POWER SUPPLY  
Rated Voltage  
Voltage Range  
Quiescent Current  
±15  
ꢀ
ꢀ
V
V
mA  
±13  
±20  
±7.5  
ꢀ
ꢀ
ꢀ
ꢀ
±6.5  
TEMPERATURE RANGE  
Specification  
B and C Grades  
S Grade  
–25  
–55  
+85  
+125  
ꢀ
°C  
°C  
Operating  
B and C Grades  
S Grade  
Storage  
–40  
–55  
–65  
+85  
+125  
+150  
ꢀ
ꢀ
ꢀ
ꢀ
°C  
°C  
°C  
ꢀ
Specification the same as for VFC320BP.  
NOTES: (1) A 25% duty cycle at full scale (0.25mA input current) is recommended where possible to achieve best linearity. (2) Determined by RIN and full scale current range  
constraints. (3) Adjustable to zero. See Offset and Gain Adjustment section. (4) Linearity error at any operating frequency is defined as the deviation from a straight line drawn between  
the full scale frequency and 0.1% of full scale frequency. See Discussion of Specifications section. (5) When offset and gain errors are nulled, at an operating temperature, the linearity  
error determines the final accuracy. (6) For e1 = 0 typical linearity errors are: 0.01% at 10kHz, 0.2% at 100kHz, 0.1% at 1MHz. (7) Exclusive of external components’ drift.  
(8) FSR = Full Scale Range (corresponds to full scale and full scale input voltage.) (9) Positive drift is defined to be increasing frequency with increasing temperature.  
(10) One pulse of new frequency plus 50ns typical.  
VFC320  
2
SBVS017A  
1234567...12

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