Datasheet > VFC320BM2

VFC320BM2

更新时间： 2024-02-18 08:24:33

品牌	Logo	应用领域
德州仪器 - TI		转换器
页数	文件大小	规格书
12页	234K
描述
Voltage-to-Frequency and Frequency-to-Voltage CONVERTER

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技术参数
数据手册

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VFC320BM2 技术参数

是否无铅：	含铅	生命周期：	Obsolete
零件包装代码：	SMT	包装说明：	,
针数：	10	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.67	转换器类型：	VOLTAGE TO FREQUENCY CONVERTER
JESD-30 代码：	O-MBCY-W10	最大线性误差 (EL)：	0.03%
最大负电源电压：	-20 V	最小负电源电压：	-13 V
标称负供电电压：	-15 V	功能数量：	1
端子数量：	10	最大工作频率：	1 MHz
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	METAL	封装形状：	ROUND
封装形式：	CYLINDRICAL	认证状态：	Not Qualified
最大供电电压：	20 V	最小供电电压：	13 V
标称供电电压：	15 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	WIRE	端子位置：	BOTTOM
Base Number Matches：	1

VFC320BM2 数据手册

The operation of the VFC320 as a highly linear frequency-

to-voltage converter, follows the same theory of operation as

the voltage-to-frequency converter. e₁and e₂are shorted and

F_INis disconnected from V_OUT. F_INis then driven with a

signal which is sufficient to trigger comparator A. The one-

shot period will then be determined by C₁as before, but the

cycle repetition frequency will be dictated by the digital

input at F_IN.

C₂

Integrator Capacitor

Gain Adjustment

I_IN

V_IN

R₁

R₃

R₄

+15V

Input

Amp

(1)

12 +V_CC

R₅

(1)

–V_CC

DUTY CYCLE

–15V

Offset Adj.

The duty cycle (D) of the VFC is the ratio of the one-shot

period (t₂) or pulse width, PW, to the total VFC period (t₁+

t₂). For the VFC320, t₂is fixed and t₁+ t₂varies as the input

voltage. Thus the duty cycle, D, is a function of the input

voltage. Of particular interest is the duty cycle at full scale

frequency, D_FS, which occurs at full scale input. D_FSis a user

determined parameter which affects linearity.

C₁

One-shot

Capacitor

One-

shot

+V_PU

R₂

f_OUT

Pin numbers in squares

refer to DIP package.

NOTE: (1) Bypass with 0.01µF

t₂

D_FS

= PW • f_FS

FIGURE 7. Connection Diagram for V/F Conversion,

Negative Input Voltages.

t₁+ t₂

Best linearity is achieved when D_FSis 25%. By reducing

equations (7) and (9) it can be shown that

EXTERNAL COMPONENT SELECTION

In general, the design sequence consists of: (1) choosing

f_MAX, (2) choosing the duty cycle at full scale (D_FS= 0.25

typically), (3) determining the input resistor, R₁(Figure 4),

(4) calculating the one-shot capacitor, C₁, (5) selecting the

integrator capacitor C₂, and (6) selecting the output pull-up

resistor, R₂.

I_INmax

1mA

V_INmax / R₁

1mA

D_FS

Thus D_FS= 0.25 corresponds to I_INmax = 0.25mA.

INSTALLATION AND

OPERATING INSTRUCTIONS

VOLTAGE-TO-FREQUENCY CONVERSION

Input Resistors R₁and R₃

The input resistance (R₁and R₃in Figures 6 and 7) is

calculated to set the desired input current at full scale input

voltage. This is normally 0.25mA to provide a 25% duty

cycle at full scale input and output. Values other than D_FS

0.25 may be used but linearity will be affected.

The VCF320 can be connected to operate as a V/F converter

that will accept either positive or negative input voltages, or

an input current. Refer to Figures 6 and 7.

The nominal value is R₁is

V_INmax

C₂

Integrator Capacitor

R₁=

Gain Adjustment

0.25mA

(10)

If gain trimming is to be done, the nominal value is reduced

by the tolerance of C₁and the desired trim range. R₁should

have a very-low temperature coefficient since its drift adds

directly to the errors in the transfer function.

I_IN

V_IN

R₃

R₁

R₄

+15V

Input

Amp

(1)

12 +V_CC

R₅

(1)

One-Shot Capacitor, C₁

–V_CC

–15V

This capacitor determines the duration of the one-shot pulse.

From equation (9) the nominal value is

Offset Adj.

C₁

One-shot

capacitor

One-

shot

V_IN

C_{1 NOM}

+V_PU

7.5 R₁f_OUT

(11)

R₂

f_OUT

For the usual 25% duty at f_MAX= V_IN/R₁= 0.25mA there is

approximately 15pF of residual capacitance so that the

design value is

Pin numbers in squares

refer to DIP package.

NOTE: (1) Bypass with 0.01µF

33 • 10⁶

FIGURE 6. Connection Diagram for V/F Conversion,

Positive Input Voltages.

C₁(pF) =

– 15

f_FS

(12)

VFC320

SBVS017A

1...3 4 567 8 9...12

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