standard value to assure that the integrator waveform volt-
age is within acceptable limits. Good dielectric absorption
properties are required to achieve best linearity. Mylar®,
polycarbonate, mica, polystyrene, Teflon® and glass types
are appropriate choices. The choice in a given application
will depend on the particular value and size considerations.
Ceramic capacitors vary considerably from type to type and
some produce significant nonlinearities. Polarized capaci-
tors should not be used.
“Shortened Output Pulses”). This minimizes power dissipa-
tion over the full frequency range and provides the fastest
logic edge at the beginning of the output pulse, where it is
most desirable.
Interface to a logic circuit would normally be made using a
pull-up resistor to the logic power supply. Selection of the
pull-up resistor should be made such that no more than
15mA flows in the output transistor. The actual choice of the
pull-up resistor may depend on the full-scale frequency and
the stray capacitance on the output line. The rising edge of
an output pulse is determined by the RC time constant of the
pull-up resistor and the stray capacitance. Excessive capaci-
tance will produce a rounding of the output pulse rising
edge, which may create problems driving some logic cir-
cuits. If long lines must be driven, a buffer or digital line
transmitter circuit should be used.
Deviation from the nominal recommended +1V to –0.75V
integrator voltage (as controlled by the integrator capacitor
value) is permissible and will have a negligible effect on
VFC operation. Certain situations may make deviations
from the suggested integrator swing highly desirable. Smaller
integrator voltages, for instance, allow more “headroom” for
averaging noisy input signals. The VFC is a fully integrating
input converter, able to reject large levels of interfering
noise. This ability is limited only by the output voltage
swing range of the integrator amplifier. By setting a small
integrator voltage swing using a large CINT value, larger
levels of noise can be integrated without integrator output
saturation and loss of accuracy. For instance, with a 50kHz
full-scale output and CINT = 0.1µF, the circuit in Figure 1
can accurately average an input through the full 0 to 10V
input range with 1Vp-p superimposed 60Hz noise.
The synchronized nature of the VFC100 makes viewing its
output on an oscilloscope somewhat tricky. Since all output
pulses align with the clock, it is best to trigger and view the
clock on one of the input channels; the output can then be
viewed on another oscilloscope channel. Depending on the
VFC input voltage, the output waveform may appear as if
the oscilloscope is not properly triggered. The output might
best be visualized by imagining a constant output frequency
which is locked to a submultiple of the clock frequency with
occasional extra pulses or missing pulses to create the
necessary average frequency. It is these extra or missing
pulses that make the output waveform appear as if the
oscilloscope is not properly triggered. This is normal. Ex-
perimentation with the input voltage and oscilloscope trig-
gering generally allows a stable view of the output and
provides an understanding of its nature.
The integrator output voltage should not be allowed to
exceed +12V or –0.2V, otherwise saturation of the opera-
tional amplifier could cause inaccuracies. Operation with
positive power supplies less than +15V will limit the output
swing of the integrator operational amplifier. Smaller inte-
grator voltage waveforms may be required to avoid output
saturation of the integrator amplifier. See “Power Supply
Considerations” for information on low voltage operation.
SHORTENED OUTPUT PULSES
The maximum integrator voltage swing requirement is nearly
symmetrical about the comparator threshold voltage (see
Figure 12). One-third greater swing is required above the
threshold than below it. Maximum demand on positive
integrator swing occurs at low scale, while the negative
swing is greatest just below full scale.
In normal operation, the negative output pulse duration is
equal to one period of the clock input. Shorter output pulses
may be useful in driving optical couplers or transformers for
voltage isolation or noise rejection. This can be accom-
plished by connecting capacitor COS as shown in Figure 5.
Pin 9 may be connected to +VCC, deactivating the output
one-shot circuit. The value of COS is chosen according to the
curve in Figure 6. Output pulses cannot be made to exceed
one clock period in duration. Thus, a COS value which would
create an output pulse which is longer than one period of the
clock will have the same effect as disabling the one-shot,
causing the output pulse to last one clock period. The
minimum practical pulse width of the one-shot circuit is
approximately 100ns. Using COS to generate shorter output
pulses does not affect the output frequency or the gain
equation.
CLOCK INPUT
The clock input is TTL and CMOS-compatible. Its input
threshold is approximately 1.4V (two diode voltage drops)
referenced to digital ground (pin 12). The clock “high” input
may be standard TLL or may be as high as +VCC – 2V. A
CMOS clock should be powered from a voltage source at
least 2V below the VFC100’s +VCC to prevent overdriving
the clock input. Alternatively, a resistive voltage divider
may be used to limit the clock voltage swing to +VCC – 2V
maximum. The clock input has a high input impedance, so
no special drivers are required. Rise time in the transition
region from 0.8V to 2V must be less than 2µs for proper
operation.
REFERENCE VOLTAGE
Excellent gain drift is achieved by use of a precision internal
5V reference. This reference is brought to an external pin
and can be used for a variety of purposes. It is used to offset
the noninverting comparator input in voltage-to-frequency
mode (although a precise voltage is not required for this
function). The reference is very useful for handling bipolar
OUTPUT
The frequency output is an open collector current-sink
transistor. Output pulses are active low such that the output
transistor is on only during the reset integration period (see
®
6
VFC100
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