5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 计数器> V62/04702-01XE
V62/04702-01XE PDF预览

V62/04702-01XE

更新时间： 2024-02-23 06:47:57
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
14页 395K
描述
HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER

阅读下载

中文翻译

获取价格

V62/04702-01XE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：GREEN, PLASTIC, SOIC-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.23
Is Samacsys：N计数方向：DOWN
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：10000000 Hz
最大I（ol）：0.0052 A工作模式：SYNCHRONOUS
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TR
峰值回流温度（摄氏度）：260电源：2/6 V
最大电源电流（ICC）：0.08 mAProp。Delay @ Nom-Sup：64 ns
传播延迟（tpd）：450 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Counters
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：3.91 mm最小 fmax：12 MHz
Base Number Matches：1

V62/04702-01XE 数据手册

 浏览型号V62/04702-01XE的Datasheet PDF文件第2页浏览型号V62/04702-01XE的Datasheet PDF文件第3页浏览型号V62/04702-01XE的Datasheet PDF文件第4页浏览型号V62/04702-01XE的Datasheet PDF文件第5页浏览型号V62/04702-01XE的Datasheet PDF文件第6页浏览型号V62/04702-01XE的Datasheet PDF文件第7页 
ꢀ
ꢁ
ꢂ
ꢃ
ꢄꢋ ꢌꢄ ꢈꢍꢊꢉ ꢉꢁ ꢀꢎ ꢏ ꢍ ꢐꢏ ꢌ ꢋ  
ꢄ
ꢀ
ꢃ
ꢅ
ꢆ
ꢅ
ꢇ
ꢈ
ꢉ
ꢊ
ꢀ
ꢖ
ꢑ
ꢈ
ꢍ
ꢒ
ꢓ
ꢌ
ꢉ
ꢍ
ꢔ
ꢕꢀ  
ꢄ
ꢖ
ꢏ
ꢕ
ꢏ
ꢗ
ꢍ
ꢁ
ꢏ
ꢘ
ꢕ
ꢀ
ꢏ
ꢗ
ꢕ
ꢒ
ꢉ
SCLS548 − DECEMBER 2003  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
Balanced Propagation Delay and Transition  
Times  
Significant Power Reduction Compared to  
LSTTL Logic ICs  
D
D
D
D
D
D
Extended Temperature Performance of  
−40°C to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
V
Voltage = 2 V to 6 V  
CC  
D
High Noise Immunity N or N = 30% of  
IL  
IH  
V
, V  
= 5 V  
CC CC  
Enhanced Product-Change Notification  
M PACKAGE  
(TOP VIEW)  
†
Qualification Pedigree  
Synchronous or Asynchronous Preset  
CP  
MR  
TE  
V
CC  
PE (SYNC)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
Cascadable in Synchronous or Ripple  
Mode  
TC  
P7  
P6  
P5  
D
Fanout (Over Temperature Range)  
− Standard Outputs . . . 10 LSTTL Loads  
− Bus Driver Outputs . . . 15 LSTTL Loads  
P0  
P1  
P2  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
P3  
10 P4  
PL (ASYNC)  
GND  
9
description/ordering information  
The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage  
synchronous down counter with a single output, which is active when the internal count is zero. The device  
contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for  
clearing the counter to its maximum count, and for presetting the counter either synchronously or  
asynchronously. All control inputs and the terminal count (TC) output are active-low logic.  
In normal operation, the counter is decremented by one count on each positive transition of the clock (CP)  
output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches  
zero, if TE is low, and remains low for one full clock period.  
When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counter on  
the next positive clock transition, regardless of the state of TE. When the asynchronous preset enable (PL) input  
is low, data at the P0−P7 inputs asynchronously are forced into the counter, regardless of the state of the PE, TE,  
or CP inputs. Inputs P0−P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset  
(MR) input is low, the counter asynchronously is cleared to its maximum count of 255 , regardless of the state of  
10  
any other input. The precedence relationship between control inputs is indicated in the truth table.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
−40°C to 125°C  
SOIC − M Tape and reel  
CD74HC40103QM96EP  
HC40103QEP  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢊ
ꢊ
ꢖ
ꢏ
ꢨ
ꢁ
ꢣ
ꢗ
ꢀ
ꢡ
ꢒ
ꢢ
ꢋ
ꢜ
ꢏ
ꢚ
ꢕ
ꢛ
ꢁ
ꢓ
ꢒ
ꢓ
ꢙ
ꢚ
ꢤ
ꢛ
ꢜ
ꢢ
ꢝ
ꢞ
ꢟ
ꢟ
ꢠ
ꢠ
ꢙ
ꢙ
ꢜ
ꢜ
ꢚ
ꢚ
ꢙ
ꢡ
ꢡ
ꢥ
ꢢ
ꢣ
ꢝ
ꢝ
ꢤ
ꢤ
ꢚ
ꢠ
ꢟ
ꢞ
ꢡ
ꢡ
ꢜ
ꢛ
ꢥ
ꢒꢤ  
ꢣ
ꢦ
ꢡ
ꢧ
ꢙ
ꢢ
ꢟ
ꢡ
ꢠ
ꢙ
ꢠ
ꢜ
ꢝ
ꢚ
ꢣ
ꢨ
ꢟ
ꢚ
ꢠ
ꢠ
ꢤ
ꢡ
ꢩ
Copyright 2003, Texas Instruments Incorporated  
ꢝ
ꢜ
ꢢ
ꢠ
ꢜ
ꢝ
ꢞ
ꢠ
ꢜ
ꢡ
ꢥ
ꢙ
ꢛ
ꢙ
ꢢ
ꢤ
ꢝ
ꢠ
ꢪ
ꢠ
ꢤ
ꢝ
ꢜ
ꢛ
ꢫ
ꢟ
ꢋ
ꢚ
ꢞ
ꢤ
ꢡ
ꢠ
ꢟ
ꢚ
ꢨ
ꢟ
ꢝ
ꢨ
ꢬ
ꢟ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢝ
ꢝ
ꢟ
ꢚ
ꢠ
ꢭ
ꢩ
ꢊ
ꢝ
ꢜ
ꢨ
ꢣ
ꢢ
ꢠ
ꢙ
ꢜ
ꢚ
ꢥ
ꢝ
ꢜ
ꢢ
ꢤ
ꢡ
ꢡ
ꢙ
ꢚ
ꢮ
ꢨ
ꢜ
ꢤ
ꢡ
ꢚ
ꢜ
ꢠ
ꢚ
ꢤ
ꢢ
ꢤ
ꢡ
ꢡ
ꢟ
ꢝ
ꢙ
ꢧ
ꢭ
ꢙ
ꢚ
ꢢ
ꢧ
ꢣ
ꢨ
ꢤ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

中文翻译

下载PDF

与V62/04702-01XE相关器件

型号 品牌 获取价格 描述 数据表
V62/04703-01XE TI

获取价格

 		HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS
V62/04703-01YE TI

获取价格

 		HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS
V62/04704-01XE TI

获取价格

 		QUADRUPLE 2-INPUT POSITIVE-AND GATES
V62/04705-01XE TI

获取价格

 		3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS
V62/04706-01XE TI

获取价格

 		3.3-V ABT 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
V62/04707-01XE TI

获取价格

 		3.3-V ABT 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
V62/04708-01XE TI

获取价格

 		3.3-V ABT 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
V62/04709-01XE TI

获取价格

 		3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
V62/04709-02YE TI

获取价格

 		3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
V62/04710-01XE TI

获取价格

 		16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

与V62/04702-01XE相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证