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V048F320T009 PDF预览

V048F320T009

更新时间： 2024-01-28 01:01:41
品牌 Logo 应用领域
VICOR /
页数 文件大小 规格书
14页 408K
描述
VI Chip - PRM-AL Pre-Regulator Module

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V048F320T009 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：MODULE
包装说明：ROHS COMPLIANT PACKAGE-9针数：9
Reach Compliance Code：not_compliantECCN代码：EAR99
风险等级：5.84模拟集成电路 - 其他类型：DC-DC REGULATED POWER SUPPLY MODULE
最大输入电压：55 V最小输入电压：26 V
JESD-30 代码：R-XDMA-X9JESD-609代码：e4
湿度敏感等级：5功能数量：1
输出次数：1端子数量：9
最大输出电压：36.67 V最小输出电压：17.33 V
封装主体材料：UNSPECIFIED封装形状：RECTANGULAR
封装形式：MICROELECTRONIC ASSEMBLY峰值回流温度（摄氏度）：225
认证状态：Not Qualified表面贴装：NO
技术：HYBRID端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：UNSPECIFIED端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED微调/可调输出：YES
Base Number Matches：1

V048F320T009 数据手册

 浏览型号V048F320T009的Datasheet PDF文件第7页浏览型号V048F320T009的Datasheet PDF文件第8页浏览型号V048F320T009的Datasheet PDF文件第9页浏览型号V048F320T009的Datasheet PDF文件第11页浏览型号V048F320T009的Datasheet PDF文件第12页浏览型号V048F320T009的Datasheet PDF文件第13页 
PRELIMINARY  
(continued)  
V•I Chip Pre-Regulator Module  
Application Information  
OVP – Overvoltage Protection  
Adjusting current limit  
The output Overvoltage Protection set point of the P048K048T24AL is  
factory preset for 56 V. If this threshold is exceeded the output shuts  
down and a restart sequence is initiated, also indicated by PC pulsing.  
If the condition that causes OVP is still present, the unit will again shut  
down. This cycle will be repeated until the fault condition is removed.  
The OVP set point may be set at the factory to meet unique high  
voltage requirements.  
The current limit can be lowered by placing an external resistor  
between the IL and SG ports (see figure 18 for resistor values). With  
the IL port open-circuit, the current limit is preset to be within the  
range specified in the output specifications table on Page 4.  
PRM output power versus VTM output power  
100.00  
10.00  
1.00  
As shown in Figure 17, the P048F048T24AL is rated to deliver 5 A  
maximum, when it is delivering an output voltage in the range from  
26 V to 48 V, and 240 W, maximum, when delivering an output  
voltage in the range from 48 V to 55 V. When configuring a PRM for  
use with a specific VTM, refer to the appropriate VTM data sheet. The  
VTM input power can be calculated by dividing the VTM output power  
by the VTM efficiency (available from the VTM data sheet). The input  
power required by the VTM should not exceed the output power  
rating of the PRM.  
1
2
3
4
5
Desired PRM Output Current Limit (A)  
5.1  
5.0  
4.9  
4.8  
4.7  
Figure 18 — Calculated external resistor value for adjusting current limit,  
actual value may vary.  
Safe Operating Area  
4.6  
Input fuse recommendations  
4.5  
4.4  
4.3  
A fuse should be incorporated at the input to the PRM, in series with  
the +IN port. A fast acting fuse, NANO2 FUSE 451/453 Series 10 A  
125 V, or equivalent, may be required to meet certain safety agency  
Conditions of Acceptability. Always ascertain and observe the safety,  
regulatory, or other agency specifications that apply to your specific  
application.  
~
~
20  
0
22 24 26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52 54 56 58 60  
Factorized Bus Voltage (Vf)  
Product safety considerations  
Figure 17 — P048K048T24AL rating based on Factorized Bus voltage  
If the input of the PRM is connected to SELV or ELV circuits, the output  
of the PRM can be considered SELV or ELV respectively.  
If the input of the PRM is connected to a centralized DC power system  
where the working or float voltage is above SELV, but less than or  
equal to 75 V, the input and output voltage of the PRM should be  
classified as a TNV-2 circuit and spaced 1.3 mm from SELV circuitry or  
accessible conductive parts according to the requirements of UL60950,  
CSA 22.2 60950, EN60950, and IEC60950.  
The Factorized Bus voltage should not exceed an absolute limit of  
55 V, including steady state, ripple and transient conditions. Exceeding  
this limit may cause the internal OVP set point to be exceeded.  
Parallel considerations  
The PR port is used to connect two or more PRMs in parallel to form a  
higher power array. When configuring arrays, PR port interconnection  
bypass capacitance must be used at ~1nF per PRM. Additionally one  
PRM should be designated as the master while all other PRMs are set  
as slaves by shorting their SC pin to SG. The PC pins must be directly  
connected (no diodes) to assure a uniform start up sequence. The  
factorized bus should be connected in parallel as well.  
Applications assistance  
Please contact Vicor Applications Engineering for assistance,  
1-800-927-9474, or email at apps@vicr.com.  
vicorpower.com  
800-735-6200  
V•I Chip Pre-Regulator Module  
P048F048T24AL  
Rev. 1.7  
Page 10 of 14  
1...7891011121314

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