Datasheet > 射频和微波 > 射频/微波开关> UPG2008TK-A

UPG2008TK-A

更新时间： 2024-01-02 08:59:26

品牌	Logo	应用领域
日电电子 - NEC		射频和微波开关射频开关微波开关光电二极管
页数	文件大小	规格书
10页	58K
描述
SPDT, 500MHz Min, 2500MHz Max, 0.85dB Insertion Loss-Max, 1.50 X 1.10 MM, 0.55 MM HEIGHT, LEAD LESS, MINIMOLD PACKAGE-6

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技术参数
数据手册

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UPG2008TK-A 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	风险等级：	5.63
Is Samacsys：	N	构造：	COMPONENT
最大输入功率 (CW)：	28.06 dBm	最大插入损耗：	0.85 dB
JESD-609代码：	e6	最大工作频率：	2500 MHz
最小工作频率：	500 MHz	最高工作温度：	85 °C
最低工作温度：	-45 °C	射频/微波设备类型：	SPDT
端子面层：	Tin/Bismuth (Sn/Bi)	Base Number Matches：	1

UPG2008TK-A 数据手册

µPG2008TB

ELECTRICAL CHARACTERISTICS

(T^A= +25°C, V^cont1= +3 V, V^cont2= 0 V or V^cont1= 0 V, V^cont2= +3 V, Z^O= 50 Ω, Off chip DC blocking

capacitors value; 51 pF, unless otherwise specified)

Parameter

Insertion Loss

Symbol

L^INS

Test Conditions

f = 0.5 to 1.0 GHz

MIN.

−

TYP.

0.30

0.40

−

MAX.

Unit

0.55

0.65

0.90

−

f = to 2.0 GHz

−

f = to 2.5 GHz

−

Isolation

ISL

RLⁱⁿ

RL^out

f = 0.5 to 2.0 GHz

f = to 2.5 GHz

−

Input Return Loss

Output Return Loss

f = 0.5 to 2.0 GHz

f = to 2.5 GHz

−

f = 0.5 to 2.0 GHz

f = to 2.5 GHz

−

Input Power at 0.1 dB

Compression Point ^Note

Input Power at 1 dB

Compression Point ^Note

Switching Speed

P^{in(0.1 dB)}f = 1.0 GHz, V^cont= +3 V/0 V

23.0

−

dBm

P^{in(1 dB)}

f = 1.0 GHz, V^cont= +3 V/0 V

V^cont= +3 V/0 V, RF Non

22.0

26.5

−

dBm

t^SW

−

200

Control Current

I^cont

0.5

µA

Note P^{in(0.1 dB)}or P^{in(1 dB)}is measured the input power level when the insertion loss increase more 0.1 dB or 1 dB

than that of linear range. All other characteristics are measured in linear range.

Cautions 1. When the µPG2008TB is used it is necessary to use DC blocking capacitors for No.1 (OUT1),

No.3 (OUT2) and No.5 (IN). The value of DC blocking capacitors should be chosen to

accommodate the frequency of operation, bandwidth, switching speed and the condition with

actual board of your system.

The range of recommended DC blocking capacitor value is less than 100 pF.

2. The distance between IC’s GND pin and ground pattern of substrate should be as shorter as

possible to avoid parasitic parameters.

Data Sheet PG10193EJ01V0DS

1 234 5 6 7...10

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