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UPD44644184F5-E37-FQ1 PDF预览

UPD44644184F5-E37-FQ1

更新时间: 2023-03-15 00:00:00
品牌 Logo 应用领域
日电电子 - NEC 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
40页 366K
描述
DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

UPD44644184F5-E37-FQ1 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:15 X 17 MM, PLASTIC, BGA-165Reach Compliance Code:compliant
风险等级:5.87最长访问时间:0.45 ns
其他特性:PIPELINED ARCHITECTUREJESD-30 代码:R-PBGA-B165
JESD-609代码:e0长度:17 mm
内存密度:75497472 bit内存集成电路类型:DDR SRAM
内存宽度:18功能数量:1
端子数量:165字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX18封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.51 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:15 mm

UPD44644184F5-E37-FQ1 数据手册

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PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
μPD44644084, 44644094, 44644184, 44644364  
72M-BIT DDR II SRAM  
4-WORD BURST OPERATION  
Description  
The μPD44644084 is a 8,388,608-word by 8-bit, the μPD44644094 is a 8,388,608-word by 9-bit, the μPD44644184 is a  
4,194,304-word by 18-bit and the μPD44644364 is a 2,097,152-word by 36-bit synchronous double data rate static RAM  
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The μPD44644084, μPD44644094, μPD44644184 and μPD44644364 integrate unique synchronous peripheral circuitry  
and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K  
and K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 0.1 V power supply  
165-pin PLASTIC BGA (15 x 17)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Pipelined double data rate operation  
Common data input/output bus  
Four-tick burst for reduced address frequency  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two output clocks (C and C#) for precise flight time  
and clock skew matching-clock and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.  
User programmable impedance output  
Fast clock cycle time : 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)  
Simple control logic for easy depth expansion  
JTAG boundary scan  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M18229EJ2V0DS00 (2nd edition)  
Date Published February 2007 NS CP(N)  
Printed in Japan  
2006  
The mark <R> shows major revised points.  
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.  

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DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
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DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165
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DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
UPD44644362AF5-E33-FQ1-A RENESAS

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2MX36 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
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DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165
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