Datasheet > UPD44644095F5-E50-FQ1-A

UPD44644095F5-E50-FQ1-A

更新时间： 2023-01-15 00:00:00

品牌	Logo	应用领域
瑞萨 - RENESAS		双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
40页	370K
描述
IC,SYNC SRAM,DDR,8MX9,CMOS,BGA,165PIN,PLASTIC

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数据手册

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

μPD44644085, 44644095, 44644185, 44644365

72M-BIT DDR II SRAM SEPARATE I/O

2-WORD BURST OPERATION

Description

The μPD44644085 is a 8,388,608-word by 8-bit, the μPD44644095 is a 8,388,608-word by 9-bit, the μPD44644185 is a

4,194,304-word by 18-bit and the μPD44644365 is a 2,097,152-word by 36-bit synchronous double data rate static RAM

fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD44644085, μPD44644095, μPD44644185 and μPD44644365 integrate unique synchronous peripheral circuitry

and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K

and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 0.1 V power supply

• 165-pin PLASTIC BGA package (15 x 17)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports

• DDR read or write operation initiated each cycle

• Pipelined double data rate operation

• Separate data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.

• User programmable impedance output

• Fast clock cycle time : 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M18230EJ2V0DS00 (2nd edition)

Date Published February 2007 NS CP(N)

Printed in Japan

2006

The mark <R> shows major revised points.

The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.

12 3 4 5 6 7...40

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与UPD44644095F5-E50-FQ1-A相关器件

型号	品牌	获取价格	描述	数据表
UPD44644182AF5-E33-FQ1-A	RENESAS	获取价格	4MX18 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
UPD44644182F5-E37-FQ1	RENESAS	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165
UPD44644182F5-E37-FQ1-A	RENESAS	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
UPD44644182F5-E40-FQ1	RENESAS	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165
UPD44644182F5-E40-FQ1-A	RENESAS	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
UPD44644182F5-E50-FQ1	RENESAS	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165
UPD44644182F5-E50-FQ1-A	RENESAS	获取价格	4MX18 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165
UPD44644184F5-E37-FQ1	NEC	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165
UPD44644184F5-E37-FQ1-A	NEC	获取价格	IC,SYNC SRAM,DDR,4MX18,CMOS,BGA,165PIN,PLASTIC
UPD44644184F5-E40-FQ1	NEC	获取价格	4MX18 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

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