UCC27532-Q1
www.ti.com
SLVSCE4A –DECEMBER 2013–REVISED JANUARY 2014
2.5-A and 5-A, 35-VMAX VDD FET and IGBT Single-Gate Driver
1
FEATURES
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Renewable Energy Power Conversion
SiC FET Converters
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following
Results:
DESCRIPTION
The UCC27532-Q1 device is a single-channel high-
speed gate driver capable of effectively driving
MOSFET and IGBT power switches by up to 2.5-A
source and 5-A sink (asymmetrical drive) peak
current. Strong sink capability in asymmetrical drive
boosts immunity against parasitic Miller turnon effect.
The UCC27532-Q1 device also features a split-output
configuration where the gate-drive current is sourced
through the OUTH pin and sunk through the OUTL
pin. This pin arrangement allows the user to apply
independent turnon and turnoff resistors to the OUTH
and OUTL pins respectively and easily control the
switching slew rates.
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Device Temperature Grade 1
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C4B
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Low-Cost Gate Driver (offering optimal
solution for driving FET and IGBTs)
Superior Replacement to Discrete Transistor
Pair Drive (providing easy interface with
controller)
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CMOS Compatible Input-Logic Threshold
(becomes fixed at VDD above 18 V)
Split Outputs Allow Separate Turnon and
Turnoff Tuning
The driver has rail-to-rail drive capability and an
extremely-small propagation delay of 17 ns (typically).
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Enable with Fixed TTL Compatible Threshold
The UCC27532-Q1 device has
a
CMOS-input
High 2.5-A Source and 5-A Sink Peak-Drive
Currents at 18-V VDD
threshold-centered 55% rise and 45% fall in regards
of VDD at VDD below or equal 18 V. When VDD is
above 18 V, the input threshold remains fixed at the
maximum level.
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Wide VDD Range From 10 V up to 35 V
Input Pins Capable of Withstanding up to –5-V
DC Below Ground
The driver has an EN pin with a fixed TTL-compatible
threshold. EN is internally pulled up; pulling EN low
disables driver, while leaving it open provides normal
operation. The EN pin can be used as an additional
input with the same performance as the IN pin.
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Output Held Low When Inputs are Floating or
During VDD UVLO
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Fast Propagation Delays (17-ns typical)
Fast Rise and Fall Times
Leaving the input pin of driver open holds the output
low. The logic behavior of the driver is shown in the
Timing Diagram, Input/Output Logic Truth Table, and
Typical Application Diagrams.
(15-ns and 7-ns typical with 1800-pF Load)
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Undervoltage Lockout (UVLO)
Used as a High-Side or Low-Side Driver (if
designed with proper bias and signal isolation)
Internal circuitry on the VDD pin provides an
undervoltage-lockout function that holds the output
low until the VDD supply voltage is within operating
range.
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Low-Cost Space-Saving 6-Pin DBV (SOT-23)
Package
Operating Temperature Range of –40°C to
140°C
The UCC27532-Q1 driver is offered in a 6-pin
standard SOT-23 (DBV) package. The device
operates over a wide temperature range of –40°C to
140°C.
APPLICATIONS
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Automotive
Switch-Mode Power Supplies
DC-to-DC Converters
Solar Inverters, Motor Control, UPS
HEV and EV Chargers
Home Appliances
EN
IN
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2
3
6
5
OUTH
OUTL
VDD
4
GND
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013–2014, Texas Instruments Incorporated