TRF1121
TRF1221
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SLWS170A–APRIL 2005–REVISED DECEMBER 2005
INPUT REFERENCE REQUIREMENTS
Conditions: Signal BW = 6 MHz nom, 15 dB maximum loss IF2 SAW filter. See Figure 19
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fRef
Reference frequency
18
MHz
PPM
Vpp
Temperature stability
Customer requirements
VFR
DCfref
tFR
Ref. source input voltage(1)
Reference Input Symmetry
Reference source pulse rise time
Reference Phase Noise at 10 kΩ offset
HCMOS Output
4
4.5
5
60%
4
Waveform Duty Cycle
40%
10% to 90% of maximum voltage transition
1
nsec
fFR
–153
–150 dBc/Hz
(1) Note that for source peak-to-peak voltages of less than 4 V and dc-component other than 2.5-V degradation of the close-in phase noise
may occur. For oscillators with no dc-component, a dc-voltage may be applied using a voltage divider (see the schematic) .
AC TIMING, SERIAL BUS INTERFACE
PARAMETER
Clock to data invalid
Data valid to clock
Clock pulse width high
Clock pulse width low
Clock to enable low
Enable low to clock
Enable pulse width
TEST CONDITIONS
MIN
10
10
50
50
10
10
10
TYP
MAX
UNIT
ns
CDI
See Figure 7
See Figure 7
See Figure 7
See Figure 7
See Figure 7
See Figure 7
See Figure 7
DVC
CPWH
CPWL
CEL
ns
ns
ns
ns
ELC
ns
EPWH
ns
DIGITAL INTERFACE CHARACTERISTICS
Conditions: Signal BW = 6 MHz nom, 15 dB maximum loss IF2 SAW filter. See Figure 19
PARAMETER
Input high voltage
Input low voltage
TEST CONDITIONS
MIN TYP
MAX
5
UNIT
V
VIH
VIL
IIH
2.1
0
0.8
50
V
Input high current
Input low current
0
µA
µA
pF
V
IIL
0
–50
CI
Input capacitance
Output logic 1 voltage
Output logic 1 impedance
Output low voltage
3
VOH
ROH
VOL
0 to 100-µA load
2.4
18
0
3.6
0.4
kΩ
V
0 to –100-µA load
AUXILIARY AND CONTROL
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
V VCOenb
VLD1
External VCO enable voltage CMOS compatible Input. See Table 9
V
Lock detect voltage (PLL1)
Lock Detect Voltage (PLL2)
CMOS compatible output (active high). See Table 9
V
VLD2
CMOS compatible output (active high). See Table 9
V
IF Output On
IF Output Off
High
Low
High
Low
Low
High
Low
Low
TXON
IF Amp Enable
EXTLO2IP
EXTLO2IN
EXTLO2IP
EXTLO2IN
EXTLO2IP
EXTLO2IN
On-chip VCO2A selection
On-chip VCO2B selection
On-chip VCO2 selection
Logic level applied to EXTLOIP and EXTLOIN pins to
select either on chip VCO 2A or 2B. Pullup resistor = 200 Ω
and pulldown resistor = 1 kΩ.
Logic Level applied to EXTLOIP and EXTLOIN pins to
select the external VCO2 input
6