TRF1112
TRF1212
www.ti.com
SLWS175A–APRIL 2005–REVISED DECEMBER 2005
Dual VCO/PLL Synthesizer With IF Down-Conversion
The TRF1112 / TRF1212 are designed to function as
part of Texas Instruments 2.5-GHz and 3.5-GHz
complete radio chipsets, respectively. In the chipset,
two chips function together to double-down convert
RF frequencies to an IF frequency that is suitable for
most baseband modem ADCs. The TRF1112 /
TRF1212 performs the second down conversion from
the first IF frequency (480 MHz typical) to a final IF
frequency (20-50 MHz). The radio chipset features
sufficient linearity, phase noise and dynamic range to
work in single carrier or multi-carrier, line-of-sight or
non-line-of-sight, IEEE standard 802.16, BWIF, or
proprietary systems. Due to the modular nature of the
chipset, it is ideal for use in systems that employ
transmit or receive diversity.
FEATURES
•
Low Phase Noise
•
High Dynamic Range Image-Reject
Downconverter
•
•
Selectable IF Filters
Internal or External AGC Control With Peak
Detector and Voltage Reference
•
•
•
Analog Gain Control Range
Direct Interface to A/D
Dual VCO/PLL With On-Chip Resonator For
Double Down-Conversion Architecture
KEY SPECIFICATIONS
•
S-Band LO Frequency Range:
– TRF1112: 1700 to 2400 MHz
– TRF1212: 2400 MHz to 3550 MHz
TRF1112 / TRF1212 PIN OUT
LPCC−48 PACKAGE
(TOP VIEW)
•
UHF LO Frequency Range: 325 MHz to 460
MHz
•
•
•
Phase Noise is 0.5 RMS Typ 100 Hz to 1 MHz
Rx Noise Figure of 5 dB, Typ
UHF LO Tuning Step Size of 125 kHz With 18
MHz Reference
36
35
34
33
32
31
30
29
28
27
26
25
1
CP2O
LD1
AGCO
IFBPB
IF1IP
•
Typical Gain of 90 dB, Including 15-dB Loss
IF2 SAW Filter
Input Third Order Intercept Point > 0 dBm
Input 1-dB Compression Point > –10 dBm
Gain Control Range of 90 dB Typ
2
3
LF1
4
EN
•
•
•
IF1IN
5
FRBP
VCCD1
FR
VCCA
VCCB
VERR
VREF
VFB
6
7
8
VCCD2
CLK
9
DESCRIPTION
10
11
12
DATA
LF2
VCCC
IF2AOP
IF2AON
The TRF1112
/ TRF1212 are UHF-VHF down
converters with integrated UHF and S-band
frequency synthesizers for radio applications in the
2GHz to 4GHz range. The device integrates an
image reject mixer, IF gain blocks, automatic gain
control (AGC), and two complete phase locked loop
(PLL) circuits including: VCOs, resonator circuit,
varactors, dividers, and phase detectors.
LD2
BLOCK DIAGRAM
The detailed block diagram and the pin-out of the
ASIC are shown in Figure 1 and the Terminal
Functions table.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.