TPSM843320E
ZHCSTQ8 – JANUARY 2024
www.ti.com.cn
4 Pin Configuration and Functions
图 4-1. SIT Package 15-Pin uSiP (Top View)
表 4-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Feedback pin for output voltage regulation. Connect this pin to the midpoint of a resistor divider to set
the output voltage.
FB
1
I
AGND
BP5
2
3
4
5
—
O
O
I
Ground return for internal analog circuits
Internal 5V regulator output. Bypass this pin with a 2.2μF capacitor to AGND.
Open-drain power-good indicator
PG
MODE
A resistor to ground selects the current limit, soft-start rate, and PWM ramp amplitude.
Enable pin. Float to enable, enable and disable with an external signal, or adjust the input undervoltage
lockout with a resistor divider.
EN
6
I
Ground return for the power stage. This pin is internally connected to the source of the low-side
MOSFET.
PGND
7, 8, 9
—
Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 47nF to
100nF capacitor from VIN to PGND close to IC is required.
VIN
10
11
12
I
SW
DNC
DNC
Switch node of the module, used for monitoring only
Supply for the internal high-side MOSFET gate driver. This pin is monitoring only because the capacitor
to SW pin is integrated
BOOT
SYNC/
FSEL
Frequency select and external clock synchronization. A resistor to ground sets the switching frequency
of the device. An external clock can also be applied to this pin to synchronize the switching frequency.
13
14
15
I
VOUT
O
—
Buck output voltage. Connect output capacitors to this node.
Thermal pad connected to PGND
PAD/
PGND
(1) I = input, O = output
Copyright © 2024 Texas Instruments Incorporated
提交文档反馈
3
Product Folder Links: TPSM843320E
English Data Sheet: SLUSFH2