TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
www.ti.com.................................................................................................................................................... SGLS322D–MAY 2006–REVISED NOVEMBER 2008
NANOPOWER SUPERVISORY CIRCUITS
1
FEATURES
TPS3836, TPS3838
DBV PACKAGE
(TOP VIEW)
•
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
1
2
3
5
4
VDD
CT
•
•
Supply Current of 220 nA (Typ)
Precision Supply Voltage Supervision Range:
1.8 V, 2.5 V, 3 V, 3.3 V
GND
RESET
MR
•
•
Power-On Reset Generator With Selectable
Delay Time of 10 ms or 200 ms
Push/Pull RESET Output (TPS3836), RESET
Output (TPS3837), or
Open-Drain RESET Output (TPS3838)
TPS3837
DBV PACKAGE
(TOP VIEW)
•
•
Manual Reset
1
2
3
VDD
5
CT
5-Pin SOT-23 Package
GND
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
4
RESET
MR
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
APPLICATIONS
•
Applications Using Automotive Low-Power
DSPs, Microcontrollers, or Microprocessors
•
•
•
•
Battery-Powered Equipment
Intelligent Instruments
Wireless Communication Systems
Automotive Systems
(1) Custom temperature ranges available
DESCRIPTION
The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing
supervision, primarily for digital signal processing (DSP) and processor-based systems.
During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold
voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system
reset. The delay time starts after VDD has risen above VIT.
When CT is connected to GND, a fixed delay time of typical 10 ms is asserted. When connected to VDD, the
delay time is typically 200 ms.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.