TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
www.ti.com
SGLS322C–MAY 2006–REVISED AUGUST 2006
NANOPOWER SUPERVISORY CIRCUITS
FEATURES
APPLICATIONS
•
Applications Using Automotive Low-Power
DSPs, Microcontrollers, or Microprocessors
•
Controlled Baseline
– One Assembly Site
– One Test Site
•
•
•
•
Battery-Powered Equipment
Intelligent Instruments
Wireless Communication Systems
Automotive Systems
– One Fabrication Site
•
•
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
TPS3836, TPS3838
DBV PACKAGE
(TOP VIEW)
•
•
•
Enhanced Product-Change Notification
(1)
1
2
3
Qualification Pedigree
5
V
CT
DD
ESD Protection Exceeds 2000 V Per
GND
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
4
RESET
MR
•
•
Supply Current of 220 nA (Typ)
Precision Supply Voltage Supervision Range:
1.8 V, 2.5 V, 3 V, 3.3 V
TPS3837
DBV PACKAGE
(TOP VIEW)
•
•
Power-On Reset Generator With Selectable
Delay Time of 10 ms or 200 ms
1
2
3
V
DD
5
CT
Push/Pull RESET Output (TPS3836), RESET
Output (TPS3837), or
GND
Open-Drain RESET Output (TPS3838)
•
•
•
Manual Reset
4
RESET
MR
5-Pin SOT-23 Package
Temperature Range –55°C to 125°C
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION
The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing
supervision, primarily for digital signal processing (DSP) and processor-based systems.
During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold
voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system
reset. The delay time starts after VDD has risen above VIT.
When CT is connected to GND, a fixed delay time of typical 10 ms is asserted. When connected to VDD, the
delay time is typically 200 ms.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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