Datasheet > TP2540

TP2540

更新时间： 2023-12-06 20:01:38

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
14页	360K
描述
This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure

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TP2540 数据手册

TP2540

P-Channel Enhancement-Mode Vertical DMOS FET

Features

General Description

• –2.4V Maximum Low Threshold

• High Input Impedance

The TP2540 low-threshold, Enhancement-mode

(normally-off) transistor uses a vertical DMOS structure

and a well-proven silicon-gate manufacturing process.

This combination produces a device with the power

handling capabilities of bipolar transistors and the high

input impedance and positive temperature coefficient

inherent in MOS devices. Characteristic of all MOS

structures, this device is free from thermal runaway and

thermally induced secondary breakdown.

• 60 pF Low Input Capacitance

• Fast Switching Speeds

• Low On-Resistance

• Free from Secondary Breakdown

• Low Input and Output Leakage

Applications

Microchip’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications

where very low threshold voltage, high breakdown

voltage, high input impedance, low input capacitance,

and fast switching speeds are desired.

• Logic-Level Interfaces (Ideal for TTL and CMOS)

• Solid-State Relays

• Battery-Operated Systems

• Photovoltaic Drives

• Analog Switches

• General Purpose Line Drivers

• Telecommunication Switches

Package Type

3-lead SOT-89

3-lead TO-92

(Top view)

DRAIN

SOURCE

DRAIN

GATE

SOURCE

GATE

See Table 3-1 and Table 3-2 for pin information.

 2020 Microchip Technology Inc.

DS20006371A-page 1

12 3 4 5 6 7...14

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