TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
O
O
High-Performance Static CMOS Technology
– Three Inter-Integrated Circuit (I2C) Modules
– Multi-Master and Slave Interfaces
– Up to 400 Kbps (Fast Mode)
TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
– 24-MHz System Clock (48-MHz Pipeline)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– 7- and 10-Bit Address Capability
O
High-End Timer Lite (HET)
– 12 Programmable I/O Channels:
– 12 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
O
Integrated Memory
– 288K-Byte Program Flash
– Two Banks With 8 Contiguous Sectors
– 16K-Byte Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
– 64-Instruction Capacity
O
O
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
O
O
Operating Features
– Low-Power Modes: STANDBY and HALT
– Industrial/Automotive Temperature Ranges
12-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 μs Minimum Sample/Conversion Time
– Calibration Mode and Self-Test Features
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Digital Watchdog (DWD) Timer
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– Interrupt Expansion Module (IEM)
– System Integrity and Failure Detection
– ICE Breaker
O
O
Flexible Interrupt Handling
Expansion Bus Module (EBM) (PGE only)
– Supports 8- and 16-Bit Expansion Bus
Memory Interface Mappings
– 42 I/O Expansion Bus Pins
O
O
Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
O
O
50 Dedicated General-Purpose I/O (GIO) Pins
and 43 Additional Peripheral I/Os (PGE)
Frequency-Modulated Zero-Pin Phase-Locked
14 Dedicated General-Purpose I/O (GIO) Pins
and 43 Additional Peripheral I/Os (PZ)
Loop (FM PLL)-Based Clock Module With
Z
Prescaler
O
O
O
Sixteen External Interrupts
– Multiply-by-8 Internal FM PLL Option
Z
Compatible ROM Device (Planned)
On-Chip Scan-Base Emulation Logic,
– ZPLL Bypass Mode
O
Ten Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
(1)
IEEE Standard 1149.1 (JTAG) Test-Access
Port
O
O
O
144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
– Two Serial Communication Interfaces (SCIs)
24
– 2 Selectable Baud Rates
100-Pin Plastic Low-Profile Quad Flatpack
(PZ Suffix)
– Asynchronous/Isosynchronous Modes
– Two Standard CAN Controllers (SCC)
– 16-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
– Class II Serial Interface B (C2SIb)
– Normal 10.4 Kbps and 4X Mode 41.6 Kbps
Development System Support Tools Available
– Code Composer Studio™ Integrated
Development Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
1 The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
Copyright © 2005, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic
data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue
these products without notice.
1
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