TMS320DM6433
Digital Media Processor
SPRS343C–NOVEMBER 2006–REVISED JUNE 2008
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the technical changes made to the SPRS343B device-specific
data manual to make it an SPRS343C revision.
Scope: Applicable updates to the TMS320DM643x DMP, specifically relating to the TMS320DM6433
device, have been incorporated.
•
•
Added 660- and 700-MHz C64x+™ device speeds.
Added designators for low-power (-L) devices.
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Added "5280, 5600 MIPS" to "High-Performance Digital Signal Processor (DM6437)" bullet
In first paragraph, updated/changed the following:
Section 1.1
Section 1.2
•
–
First sentence from "With performance up to 4800 million instructions per second (MIPS) at a clock
rate of 600 MHz..." to "With performance up to 5600 million instructions per second (MIPS) with a
clock rate of 700 MHz..."
–
Fifth sentence from "The DSP core can produce...for a total of 2400 million MACs per second...or a
total of 4800 MMACS."to "The DSP core can produce...for a total of 2800 million MACs per
second...or a total of 5600 MMACS."
Section 2.6
Table 2-23, Multichannel Audio Serial Port (McASP0) Terminal Functions:
•
Updated/Changed AFSR0/DR0/GP[100] pin description from "... frame synchronization AFSX0..." to
"...frame synchronization AFSR0..."
•
Updated/Changed AFSX0/DX1/GP[107] pin description from "...frame synchronization AFSR0..." to
"...frame synchronization AFSX0..."
Table 2-20, DAC [Part of VPBE] Terminal Functions:
Updated/Changed VDDA_1P1V description
•
Section 2.8
Section 5
Updated/Changed Figure 2-10, Device Nomenclature, to reflect new device speeds and low-power
designator (-L suffix).
Added footnote to Section 5.1, Absolute Maximum Ratings Over Operating Temperature Range (Unless
Otherwise Noted)
Section 5
Updated/Changed ICDD and IDDD test conditions and footnote in Section 5.3, Electrical Characteristics Over
Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted).
Section 6.7.1
Table 6-15, PLLC1 Clock Frequency Ranges:
•
Updated/Changed PLLOUT 1.2V-CVDD max value from "700 MHz" to "600 MHz" for
-6/-5/-4/-L/-Q6/-Q5/-Q4 devices.
•
Updated/Changed SYSCLK1 1.05V-CVDD max value from "560 MHz" to "520 MHz" for -7 devices.
Section 5.2
Deleted "Future variants..." footnote from table
Section 6.7.1
Updated/Changed sentence from "TI requires EMI filter manufacturer Murata..." to "TI recommends EMI
filter manufacturer Murata..."
Section 6.7.4
Deleted "(-4, -4Q, -4S, -5, -5Q, -5S, -6)" from Table 6-19 title, Timing Requirements for MXI/CLKIN.
2 Device Overview
2.1 Device Characteristics
Table 2-1, provides an overview of the TMS320DM6433 DSP. The tables show significant features of the
DM6433 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the
package type with pin count.
6
Revision History
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