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TM16LR64JFN PDF预览

TM16LR64JFN

更新时间: 2024-09-24 12:22:27
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
17页 292K
描述
SYNCHRONOUS DYNAMIC RAM MODULES

TM16LR64JFN 数据手册

 浏览型号TM16LR64JFN的Datasheet PDF文件第2页浏览型号TM16LR64JFN的Datasheet PDF文件第3页浏览型号TM16LR64JFN的Datasheet PDF文件第4页浏览型号TM16LR64JFN的Datasheet PDF文件第5页浏览型号TM16LR64JFN的Datasheet PDF文件第6页浏览型号TM16LR64JFN的Datasheet PDF文件第7页 
ꢅ ꢋ ꢂ ꢌ ꢍ ꢅꢆ ꢎꢌ ꢏ ꢀ  
ꢒ ꢐ ꢅ ꢌ ꢍ ꢅꢆ ꢎꢌ ꢏ ꢀ  
SMMS710 − MAY 1998  
D
Organization:  
− TM8LR64JFN . . . 8388608 × 64 Bits  
− TM16LR64JFN . . . 16777216 × 64 Bits  
D
High-Speed, Low-Noise, Low-Voltage TTL  
(LVTTL) Interface  
D
Read Latencies 2 and 3 Supported  
D
D
Designed for 100-MHz 4-Clock Systems  
D
Supports Burst-Interleave and  
Burst-Interrupt Operations  
JEDEC 168-Pin Dual-In-Line Memory  
Module (DIMM) Without Buffer for Use With  
Socket  
D
D
D
D
D
D
Burst Length Programmable to 1, 2, 4,  
and 8  
D
TM8LR64JFN — Uses Eight 64M-Bit  
Synchronous Dynamic RAMs (SDRAMs)  
(8M × 8-Bit) in Plastic Thin Small-Outline  
Packages (TSOPs)  
Four Banks for On-Chip Interleaving  
(Gapless Access)  
Ambient Temperature Range  
0°C to 70°C  
Electroless Gold-Finished Contacts  
D
D
D
TM16LR64JFN — Uses Sixteen 64M-Bit  
SDRAMs (8M × 8-Bit) in Plastic TSOPs  
Performance Ranges:  
Pipeline Architecture  
Serial Presence-Detect (SPD) Using  
EEPROM  
Single 3.3-V Power Supply  
( 10% Tolerance)  
D
Byte-Read/Write Capability  
SYNCHRONOUS  
CLOCK CYCLE  
TIME  
ACCESS TIME  
CLOCK TO  
OUTPUT  
REFRESH  
INTERVAL  
t
t
t
t
t
REF  
CK3  
CK2  
AC3  
AC2  
’xLR64JFN-8  
8 ns  
8 ns  
10 ns  
10 ns  
6 ns  
6 ns  
6 ns  
64 ms  
64 ms  
’xLR64JFN-8A  
7.5 ns  
description  
The TM8LR64JFN is a 64M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of eight  
TMS664814DGE 8388608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package  
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number  
SMOS695).  
The TM16LR64JFN is a 128M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS664814DGE  
8388608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic TSOP mounted on a substrate with decoupling  
capacitors.  
operation  
The TM8LR64JFN operates as eight TMS664814DGE devices that are connected as shown in the  
TM8LR64JFN functional block diagram. The TM16LR64JFN operates as 16 TMS664814DGE devices  
connected as shown in the TM16LR64JFN functional block diagram.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢪꢧ ꢨ ꢞ ꢮꢟ ꢩꢬ ꢤ ꢨ ꢧ ꢡꢠ ꢪꢧ ꢭ ꢧ ꢯꢡ ꢩꢣꢧ ꢟꢥꢰ ꢔ ꢬꢤ ꢢꢤ ꢦꢥ ꢧꢢ ꢞꢨ ꢥꢞ ꢦ ꢪꢤ ꢥꢤ ꢤꢟ ꢪ ꢡꢥ ꢬꢧꢢ  
Copyright 1998, Texas Instruments Incorporated  
ꢦ ꢬꢤ ꢟ ꢮꢧ ꢡꢢ ꢪꢞ ꢨ ꢦ ꢡꢟ ꢥꢞ ꢟꢫꢧ ꢥ ꢬꢧ ꢨ ꢧ ꢩꢢ ꢡꢪ ꢫꢦꢥ ꢨ ꢲ ꢞꢥꢬ ꢡꢫꢥ ꢟꢡꢥ ꢞꢦꢧ ꢰ  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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