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TLV5580CDWR PDF预览

TLV5580CDWR

更新时间: 2024-02-13 15:07:53
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
34页 531K
描述
1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, SOIC-28

TLV5580CDWR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:TSSOP, TSSOP28,.25针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.54
最大模拟输入电压:3.5 V最小模拟输入电压:0.8 V
最长转换时间:0.0125 µs转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:R-PDSO-G28长度:9.7 mm
最大线性误差 (EL):0.9375%模拟输入通道数量:1
位数:8功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C输出位码:BINARY
输出格式:PARALLEL, 8 BITS封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP28,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified采样速率:80 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:1.2 mm
子类别:Analog to Digital Converters标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

TLV5580CDWR 数据手册

 浏览型号TLV5580CDWR的Datasheet PDF文件第3页浏览型号TLV5580CDWR的Datasheet PDF文件第4页浏览型号TLV5580CDWR的Datasheet PDF文件第5页浏览型号TLV5580CDWR的Datasheet PDF文件第7页浏览型号TLV5580CDWR的Datasheet PDF文件第8页浏览型号TLV5580CDWR的Datasheet PDF文件第9页 
TLV5580  
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER  
SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999  
electrical characteristics over recommended operating conditions with f  
of external voltage references (unless otherwise noted)  
= 80 MSPS and use  
CLK  
power supply  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
57  
3
MAX  
71  
UNIT  
AV  
DD  
AV  
DD  
L
= DV  
= 3.3 V, DRV  
= 3 V,  
DD  
DD  
= 15 pF, V = 1 MHz, –1 dBFS  
I
Operating supply current  
DV  
3.6  
7.5  
270  
210  
15  
mA  
DD  
DD  
DRV  
C
I
5
DD  
PWDN_REF = L  
213  
165  
11  
P
P
Power dissipation  
Standby power  
D
PWDN_REF = H  
mW  
STBY = H, CLK held high or low  
D(STBY)  
digital logic inputs  
PARAMETER  
High-level input current on CLK  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
I
I
AV  
AV  
= DV  
= DV  
= DRV  
= DRV  
= CLK = 3.6 V  
= 3.6 V,  
10  
µA  
IH  
DD  
DD  
DD  
DD  
Low-level input current on digital inputs  
(OE, STDBY, PWDN_REF, CLK)  
DD  
DD  
10  
µA  
IL  
Digital inputs at 0 V  
C
Input capacitance  
5
pF  
I
I
leakage current on other digital inputs (OE, STDBY, PWDN_REF) is not measured since these inputs have an internal pull-down resistor of  
IH  
4 Kto DGND.  
logic outputs  
PARAMETER  
TEST CONDITIONS  
= DRV = 3 V at I  
MIN  
TYP  
MAX  
UNIT  
AV  
DD  
= DV  
= 50 µA,  
OH  
DD  
DD  
V
V
High-level output voltage  
2.8  
V
OH  
Digital output forced high  
AV = DV = DRV  
Digital output forced low  
= 3.6 V at I = 50 µA,  
OL  
DD DD  
DD  
Low-level output voltage  
Output capacitance  
0.1  
V
OL  
C
5
pF  
µA  
O
High-impedance state output current to  
high level  
I
10  
10  
OZH  
AV  
DD  
= DV  
= DRV = 3.6 V  
DD  
DD  
High-impedance state output current to  
low level  
I
µA  
OZL  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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