THS4304
www.ti.com
SLOS436A–MARCH 2004–REVISED JULY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PINOUT DRAWING
TOP VIEW
DBV
TOP VIEW
D and DGK
+
V
V
1
2
5
4
NC
IN−
IN+
NC
S
1
2
3
4
8
7
6
5
OUT
+
V
S
V −
S
V
OUT
IN+
IN−
3
V −
S
V
OUT
NOTE: NC indicates there is no internal connection to these pins.
PACKAGING / ORDERING INFORMATION
TRANSPORT MEDIA,
QUANTITY
PACKAGED DEVICES
PACKAGE TYPE
PACKAGE MARKINGS
THS4304DBVT
THS4304DBVR
THS4304D
Tape and Reel, 250
Tape and Reel, 3000
Rails, 75
SOT-23-5
AKW
SOIC-8
—
THS4304DR
Tape and Reel, 2500
Rails, 100
THS4304DGK
THS4304DGKR
MSOP-8
AKU
Tape and Reel, 2500
DISSIPATION RATINGS
POWER RATING(2)
θJC
(°C/W)
θJA
PACKAGE
(°C/W)(1)
TA≤ 25°C
391 mW
1.02 W
TA = 85°C
156 mW
410 mW
221 mW
DBV (5)
D (8)
55
255.4
97.5
38.3
71.5
DGK (8)
180.8
553 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal
management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term
reliability.
2