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SLAS254B − MAY 2002 − REVISED NOVEMBER 2002
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of the processor connected to the ADC. Internal
reference voltages for the ADC (1.5 V and 3.5 V) are
provided.
FEATURES
D
Simultaneous Sampling of Two Single-Ended
Signals or One Differential Signal
An external reference can also be chosen to suit the dc
accuracy and temperature drift requirements of the
application. Two different conversion modes can be
selected. In the single conversion mode, a single and
simultaneous conversion can be initiated by using the
single conversion start signal (CONVST). The conversion
clock in the single conversion mode is generated internally
using a clock oscillator circuit. In the continuous
conversion mode, an external clock signal is applied to the
CONV_CLK input of the THS10082. The internal clock
oscillator is switched off in the continuous conversion
mode.
D
Integrated 16-Word FIFO
D
Signal-to-Noise and Distortion Ratio: 59 dB at
f = 2 MHz
I
D
D
D
D
D
D
D
Differential Nonlinearity Error: 1 LSB
Integral Nonlinearity Error: 1 LSB
Auto-Scan Mode for Two Inputs
3-V or 5-V Digital Interface Compatible
Low Power: 216 mW Max
5-V Analog Single Supply Operation
Internal Voltage References . . . 50 PPM/°C
and 5% Accuracy
The THS10082C is characterized for operation from 0°C
to 70°C, and the THS10082I is characterized for operation
from −40°C to 85°C.
D
Parallel µC/DSP Interface
APPLICATIONS
DA PACKAGE
(TOP VIEW)
D
D
D
D
D
Radar Applications
Communications
D0
D1
D2
D3
D4
D5
OV_FL
RESET
AINP
1
32
31
30
29
28
27
26
25
24
23
22
21
Control Applications
High-Speed DSP Front-End
Automotive Applications
2
3
AINM
4
REFIN
REFOUT
REFP
REFM
AGND
5
DESCRIPTION
6
BV
7
DD
The THS10082 is a CMOS, low-power, 10-bit, 8 MSPS
analog-to-digital converter (ADC). The speed, resolution,
bandwidth, and single-supply operation are suited for
applications in radar, imaging, high-speed acquisition, and
communications. A multistage pipelined architecture with
output error correction logic provides for no missing codes
over the full operating temperature range. Internal control
registers allow for programming the ADC into the desired
mode. The THS10082 consists of two analog inputs,
which are sampled simultaneously. These inputs can be
selected individually and configured to single-ended or
differential inputs. An integrated 16 word deep FIFO
allows the storage of data in order to take the load off
BGND
8
D6
D7
9
AV
10
11
12
13
14
15
16
DD
D8
D9
CS0
CS1
RA0
RA1
20 WR (R/W)
19
18
17
RD
DV
CONV_CLK (CONVST)
DATA_AV
DD
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002, Texas Instruments Incorporated