TDA9850P

更新时间： 2024-01-28 06:58:22

品牌	Logo	应用领域
恩智浦 - NXP		解码器
页数	文件大小	规格书
32页	207K
描述
IC SPECIALTY CONSUMER CIRCUIT, PDIP32, Consumer IC:Other

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TDA9850P 技术参数

生命周期：	Obsolete	包装说明：	SOP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.69	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	R-PDSO-G32
长度：	20.5 mm	功能数量：	1
端子数量：	32	最高工作温度：	70 °C
最低工作温度：	-20 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
座面最大高度：	2.65 mm	最大压摆率：	75 mA
最大供电电压 (Vsup)：	9.5 V	最小供电电压 (Vsup)：	8.5 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.5 mm	Base Number Matches：	1

TDA9850P 数据手册

Philips Semiconductors

Preliminary speciﬁcation

I²C-bus controlled BTSC stereo/SAP decoder

TDA9850

FUNCTIONAL DESCRIPTION

Input level adjustment

Noise detector

The composite input noise increases with decreasing

antenna signal. This makes it necessary to switch stereo

or SAP off at certain thresholds. These thresholds can be

set via the I²C-bus. With ST0 to ST3 (see Table 6) the

stereo threshold can be selected and with SP0 to SP3 the

SAP threshold. A hysteresis can be achieved via software

by making the threshold dependent of the identification

bits STP and SAPP (see Table 2).

The composite input signal is fed to the input level

adjustment stage. The control range is from

−3.5 to +4.0 dB in steps of 0.5 dB. The subaddress

control 4 of Tables 5 and 6 and the level adjust setting of

Table 10 allows an optimum signal adjustment during the

set alignment. The maximum input signal voltage is

2 V (RMS).

Mode selection

Stereo decoder

The stereo/SAP switch feeds either the L − R signal or the

SAP demodulator output signal via the internal dbx noise

reduction circuit to the dematrix/switching circuit. Table 8

shows the different switch modes provided at the output

pins OUTR and OUTL.

The output signal of the level adjustment stage is coupled

to a low-pass filter which suppresses the baseband noise

above 125 kHz. The composite signal is then fed into a

pilot detector/pilot cancellation circuit and into the MPX

demodulator. The main L + R signal passes a 75 µs fixed

de-emphasis filter and is fed into the dematrix circuit. The

decoded sub-signal L − R is sent to the stereo/SAP switch.

To generate the pilot signal the stereo demodulator uses a

PLL circuit including a ceramic resonator. The stereo

channel separation is adjusted by an automatic procedure

to be performed during set production. For a detailed

description see Section “Adjustment procedure”. The

stereo identification can be read by the I²C-bus

dbx decoder

The dbx circuit includes all blocks required for the noise

reduction system in accordance with the BTSC system

specification. The output signal is fed through a 73 µs fixed

de-emphasis circuit to the dematrix block.

SAP output

(see Table 2). Two different pilot thresholds (data

STS = 1; STS = 0) can be selected via the I²C-bus

(see Table 14).

Independent of the stereo/SAP switch, the SAP signal is

also available at pin SAP. At SAP, the SAP signal is not

dbx decoded. The capacitor at SDE provides a

recommended de-emphasis (150 µs) at SAP.

SAP demodulator

The composite signal is fed from the output of the input

level adjustment stage to the SAP demodulator circuit

through a 5f_Hband-pass filter. The demodulator level is

automatically controlled. The SAP demodulator includes

an internal field strength detector that mutes the SAP

output in the event of insufficient signal conditions. The

SAP identification signal can be read by the I²C-bus

(see Table 2).

Integrated ﬁlters

The filter functions necessary for stereo and SAP

demodulation and part of the dbx filter circuits are provided

on-chip using transconductor circuits. The required filter

accuracy is attained by an automatic filter alignment

circuit.

1995 Jun 19

1...4 5 678 9 10...32

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与TDA9850P相关器件

型号	品牌	描述	获取价格	数据表
TDA9850PN	NXP	IC SPECIALTY CONSUMER CIRCUIT, PDIP32, Consumer IC:Other	获取价格
TDA9850T	NXP	I2C-bus controlled BTSC stereo/SAP decoder	获取价格
TDA9850TD-T	ETC	BTSC/SAP Audio Decoder	获取价格
TDA9850T-T	NXP	IC SPECIALTY CONSUMER CIRCUIT, PDSO32, Consumer IC:Other	获取价格
TDA9851	NXP	I2C-bus controlled economic BTSC stereo decoder	获取价格
TDA9851T	NXP	I2C-bus controlled economic BTSC stereo decoder	获取价格

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