Datasheet > TDA8751T

TDA8751T

更新时间： 2024-02-22 21:29:55

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
24页	135K
描述
QPSK receiver

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技术参数
数据手册

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TDA8751T 技术参数

生命周期：	Obsolete	Reach Compliance Code：	compliant
风险等级：	5.84

TDA8751T 数据手册

Philips Semiconductors

Product speciﬁcation

QPSK receiver

TDA8051

FUNCTIONAL DESCRIPTION

The raw I and Q generated signals contain spurious

spikes, therefore each signal is passed through a third

order active low-pass filter (RC cell + Sallen-Key

structure), whose cut-off frequency is set by external

components. The filtered I and Q data signals are then

amplified to provide balanced buffer outputs.

The QPSK modulated signal is applied to the input as an

asymmetrical RF signal in the bandwidth 44 to 130 MHz.

The spectrum extension to this waveform must be limited

by a band-pass filter superseding the IC.

The RF input is either the LNA input, if the level is

−30 to 0 dBmVrms, or the DEMOD input if the level is

−20 to +10 dBmVrms. The amplified RF signal is then

mixed with two clocks in quadrature to provide the

base-band demodulated In-phase (I) and Quad-phase (Q)

signals.

The data sent to the PLL is loaded in bursts, framed by

signal EN. Programming clock edges, together with their

relevant data bits, are ignored until EN becomes active

(LOW). The internal latches are updated with the latest

programming data when EN returns to inactive (HIGH).

The last 14 bits only are retained within the programming

received while programming is enabled. An active clock

edge causing a shift of the data bits is generated when

EN goes HIGH while CLOCK is still LOW. The main divider

ratio and the reference divider ratio are provided via the

serial bus (see Table 1).

The VCO operates at twice the RF carrier frequency in the

bandwidth 88 - 260 MHz (one octave), therefore the

0 to 90° clocks are generated by a divider by 2.

The VCO frequency can be programmed by an integrated

PLL that tunes the external LC tank circuit.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER

V_CC

V_(max)

t_sc

MIN.

−0.3

MAX.

6.0

UNIT

supply voltage

maximum voltage on all pins except pin 9 (5 V)

maximum short circuit duration on outputs

storage temperature

−0.3

−

V_CC

T_stg

−40

−

+150

150

°C

T_j(max)

T_amb

maximum junction temperature

operating ambient temperature

tuning voltage supply

V_CC(tune)

−0.3

HANDLING

HBM ESD: The IC pins withstand 2 kV except pin 26 (1750 V).

MM ESD: The IC pins withstand 100 V except pins 2 and 31 (75 V).

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

in free air

VALUE

UNIT

R_th(j-a)

thermal resistance from junction to ambient

K/W

1999 Aug 20

1 2 3 456 7 8...24

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