TDA1545TD-T

更新时间： 2024-02-19 10:04:37

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
20页	129K
描述
IC SERIAL INPUT LOADING, 0.2 us SETTLING TIME, 16-BIT DAC, PDSO8, MINI, PLASTIC, SOT-96A, SOP-8, Digital to Analog Converter

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TDA1545TD-T 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.79
Is Samacsys：	N	转换器类型：	D/A CONVERTER
输入位码：	2'S COMPLEMENT BINARY	输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G8	长度：	4.9 mm
位数：	16	功能数量：	1
端子数量：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
座面最大高度：	1.75 mm	标称安定时间 (tstl)：	0.2 µs
最大压摆率：	4 mA	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.9 mm	Base Number Matches：	1

TDA1545TD-T 数据手册

Philips Semiconductors

Preliminary speciﬁcation

Stereo continuous calibration DAC

TDA1545A

The TDA1545A accepts input serial data formats of 16-bit

word length. Left and right data words are time

FUNCTIONAL DESCRIPTION

The basic operation of the continuous calibration DAC is

illustrated in Fig.4. The figure shows the calibration

principle (Fig.4a) and operation principle (Fig.4b). During

calibration of the MOS current source (Fig.4a) transistor

M1 is connected as a diode by applying a reference

current. The voltage V_gson the intrinsic gate-source

capacitance C_gsof M1 is then determined by the transistor

characteristics. After calibration of the drain current to the

reference value I_REF, the switch S1 is opened and S2 is

switched to the other position (Fig.4b). The gate-to-source

voltage V_gsof M1 is not changed because the charge on

C_gsis preserved. Therefore the drain current of M1 will still

be equal to I_REFand this exact duplicate of I_REFis now

available at the I_outterminal. The 32 current sources and

the spare current source of the TDA1545A are

multiplexed. The most significant bit (bit 1) must always be

first. The format of data input is shown in Figs 5 and 6.

With a LOW level on the word select input (WS) input data

is placed in the right input register and with a HIGH level

on the WS input data is placed in the left input register.

The data in the input registers is simultaneously latched in

the output registers which control the bit switches.

An internal bias current I_bias(see I_BLand I_BRin Fig.1) is

added to the full-scale output current IFS in order to

achieve the maximum dynamic range at the outputs of

OP1 and OP2 (see Fig.1). The reference input current I_REF

controls with gain AFS the current IFS which is a sink

current and with gain A_biasthe I_biaswhich is a source

current (note 1). The current I_REFis proportional to V_DDso

the I_FSand I_biaswill also be proportional to V_DD(note 2)

because A_FSand A_biasare constant.

continuously calibrated (see Fig.1).

The spare current is included to allow for continuous

convertor operation. The output of one calibrated source is

connected to an 11-bit binary current divider consisting of

2048 transistors. A symmetrical offset decoding principle

is incorporated and arranges the bit switching in such a

way that the zero-crossing is performed only by the LSB

currents.

The reference output voltage V_REFin Fig.1 is ²⁄₃V_DD. In this

way the maximum dynamic range is achieved over the

entire power supply range. The tolerance of the reference

input current in Fig.1 depends on the tolerance of the

resistors R3, R4 and R_REF(note 3).

Notes to the functional description

1. I_FS= A_FS× I_REFand I_bias= A_bias× I_REF

V_DD1

I _FS1

I _bias1

-------------

V_DD2

----------

I_FS2

-------------

I_bias2

V_DD

---------------------------------------------------------------------------------------------------------

R3 + ∆R3 + R4 + ∆R4 + R_REF+ ∆R_REF

3. ∆I_REF= I_REF

–

1997 Sep 04

1...3 4 567 8 9...20

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与TDA1545TD-T相关器件

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TDA1547P	NXP	IC DUAL, SERIAL INPUT LOADING, 1-BIT DAC, PDIP32, PLASTIC, SOT-232A, SDIP-32, Digital to A	获取价格
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TDA1548TD	NXP	IC SERIAL INPUT LOADING, 20-BIT DAC, PDSO28, Digital to Analog Converter	获取价格

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