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TC9400CPD PDF预览

TC9400CPD

更新时间: 2024-01-20 01:31:22
品牌 Logo 应用领域
美国微芯 - MICROCHIP 转换器模拟特殊功能转换器光电二极管PC
页数 文件大小 规格书
20页 504K
描述
Voltage-to-Frequency/Frequency-to-Voltage Converters

TC9400CPD 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:SDIP, SDIP24,.3针数:24
Reach Compliance Code:unknown风险等级:5.73
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:R-PDIP-T24
长度:22 mm位数:1
功能数量:1端子数量:24
最高工作温度:85 °C最低工作温度:-35 °C
封装主体材料:PLASTIC/EPOXY封装代码:SDIP
封装等效代码:SDIP24,.3封装形状:RECTANGULAR
封装形式:IN-LINE, SHRINK PITCH电源:5 V
认证状态:Not Qualified座面最大高度:4.5 mm
子类别:Other Converters最大压摆率:40 mA
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:THROUGH-HOLE端子节距:1.778 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

TC9400CPD 数据手册

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TC9400/9401/9402  
4.3  
Freq/2 Out  
4.8  
IIN  
This output is an open drain N-channel FET, which pro-  
vides a square wave one-half the frequency of the  
pulse frequency output. The FREQ/2 OUT output will  
change state on the rising edge of PULSE FREQ OUT.  
This output requires a pull-up resistor and interfaces  
directly with MOS, CMOS, and TTL logic.  
The inverting input of the operational amplifier and the  
summing junction when connected in the V/F mode. An  
input current of 10µA is specified, but an over range  
current up to 50µA can be used without detrimental  
effect to the circuit operation. I connects the summing  
IN  
junction of an operational amplifier. Voltage sources  
cannot be attached directly, but must be buffered by  
external resistors.  
4.4  
Output Common  
The sources of both the FREQ/2 OUT and the PULSE  
FREQ OUT are connected to this pin. An output level  
4.9  
VREF  
swing from the drain voltage to ground, or to the V  
A reference voltage from either a precision source, or  
SS  
supply, may be obtained by connecting this pin to the  
appropriate point.  
the V supply is applied to this pin. Accuracy of the  
TC9400 is dependent on the voltage regulation and  
temperature characteristics of the reference circuitry.  
SS  
4.5  
RBIAS  
Since the TC9400 is a charge balancing V/F converter,  
the reference current will be equal to the input current.  
For this reason, the DC impedance of the reference  
voltage source must be kept low enough to prevent lin-  
earity errors. For linearity of 0.01%, a reference imped-  
ance of 200W or less is recommended. A 0.1µF bypass  
An external resistor, connected to V , sets the bias  
point for the TC9400. Specifications for the TC9400 are  
based on R  
noted.  
SS  
= 100k±10%, unless otherwise  
BIAS  
Increasing the maximum frequency of the TC9400  
beyond 100kHz is limited by the pulse width of the  
capacitor should be connected from V  
to ground.  
REF  
pulse output (typically 3µsec). Reducing R  
decrease the pulse width and increase the maximum  
operating frequency, but linearity errors will also  
will  
BIAS  
4.10 VREF Out  
The charging current for C  
is supplied through this  
REF  
increase. R  
can be reduced to 20k, which will  
pin. When the Op Amp output reaches the threshold  
level, this pin is internally connected to the reference  
BIAS  
typically produce a maximum full scale frequency of  
500kHz.  
voltage and a charge, equal to V  
x C  
, is removed  
REF  
REF  
from the integrator capacitor. After about 3µsec, this pin  
is internally connected to the summing junction of the  
4.6  
Amplifier Out  
Op Amp to discharge C . Break-before-make switch-  
ing ensures that the reference voltage is not directly  
applied to the summing junction.  
REF  
This pin is the output stage of the operational amplifier.  
During V/F operation, a negative going ramp signal is  
available at this pin. In the F/V mode, a voltage  
proportional to the frequency input is generated.  
4.7  
Zero Adjust  
This pin is the non-inverting input of the operational  
amplifier. The low frequency set point is determined by  
adjusting the voltage at this pin.  
2002 Microchip Technology Inc.  
DS21483B-page 9  

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