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TC74LVX74F_07 PDF预览

TC74LVX74F_07

更新时间: 2024-09-26 03:18:31
品牌 Logo 应用领域
东芝 - TOSHIBA 触发器
页数 文件大小 规格书
8页 242K
描述
Dual D-Type Flip-Flop with Preset and Clear

TC74LVX74F_07 数据手册

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TC74LVX74F/FN/FT  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74LVX74F,TC74LVX74FN,TC74LVX74FT  
Dual D-Type Flip-Flop with Preset and Clear  
Note: xxxFN (JEDEC SOP) is not available in  
Japan.  
The TC74LVX74F/ FN/ FT is a high-speed CMOS D-flip flop  
fabricated with silicon gate CMOS technology. Designed for use  
TC74LVX74F  
in 3-V systems, it achieves high-speed operation while  
maintaining the CMOS low power dissipation.  
This device is suitable for low-voltage and battery operated  
systems.  
The signal level applied to the D input is transferred to Q  
output during the positive going transition of the CK pulse.  
CLR and PR are independent of the CK and are  
accomplished by setting the appropriate input low.  
An input protection circuit ensures that 0 to 5.5V can be  
TC74LVX74FN  
applied to the input pins without regard to the supply voltage.  
This device can be used to interface 5V to 3V systems and two  
supply systems such as battery back up. This circuit prevents  
device destruction due to mismatched supply and input voltages.  
Features  
High-speed: f  
= 145 MHz (typ.) (V  
= 3.3 V)  
max  
CC  
Low power dissipation: I  
= 2 μA (max) (Ta = 25°C)  
CC  
TC74LVX74FT  
Input voltage level: V = 0.8 V (max) (V  
= 3 V)  
= 3 V)  
IL  
CC  
CC  
V
IH  
= 2.0 V (min) (V  
Power-down protection provided on all inputs  
Balanced propagation delays: t  
t
pHL  
pLH  
Pin and function compatible with 74HC74  
Weight  
SOP14-P-300-1.27A  
SOL14-P-150-1.27  
TSSOP14-P-0044-0.65A  
: 0.18 g (typ.)  
: 0.12 g (typ.)  
: 0.06 g (typ.)  
1
2007-10-17  

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