Datasheet > T0514TL

T0514TL

更新时间： 2022-02-26 14:44:56

品牌	Logo	应用领域
竹懋 - CITC		/
页数	文件大小	规格书
9页	905K
描述
Ultra-Low Capacitance ESD Protection Device

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T0514TL 数据手册

T0514TL

Ultra-Low Capacitance ESD Protection Device

Chip Integration Technology Corporation

Application Information

Pin Connection in PCB

PCB Layout Guidelines

T0514TL is capable to provide ESD protection for

four data lines simultaneously. The pin connection is

shown in Figure 1.

For optimum ESD protection and the whole circuit

performance, the following PCB layout guidelines are

recommended:

Four parallel data lines, from inner IC to I/O port

T0514TL GND pin to the PCB GND rail path

should be as short as possible. It could reduce the

ESD transient return path to GND.

connector, could connect to

four I/O pins

T0514TL

directly. Pin 2 of T0514TL is the negative reference

pin, which should connect to the GND of PCB. The

connection wires should be as short as possible in

order to minimize the parasitic inductance.

I/O1

The vias connecting

T0514TL VCC & GND pins

to the PCB VCC & GND should be wide.

Place as close to the connector port as

T0514TL

possible. It could reduce the parasitic inductance

and restrict ESD couplinginto adjacent traces.

Avoid running critical signals near board edges.

To Connector

I/O2

To Inner IC

VCC

GND

I/O3

To Connector

I/O4

To Inner IC

Figure 2 T0514TL Layout Guideline

Figure 1 T0514TL pin connection in PCB

Universal Serial Bus ESD Protection

V_BUS

R_T

D+

USB

R_T

C_T

D-

Port1

GND

C_T

USB

T0514TL

Controller

C_T

V_BUS

D+

C_T

R_T

USB

Port2

D-

R_T

GND

Document ID : DS-22V05

Revised Date : 2016/08/30

Revision : C

1 2 345 6 7...9

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