Datasheet > SYN100E137JC-TR

SYN100E137JC-TR

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
5页	64K
描述
100E SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC28

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SYN100E137JC-TR 数据手册

SY10E137

Micrel, Inc.

SY100E137

8-BIT RIPPLE

COUNTER

SY10E137

SY100E137

FEATURES

DESCRIPTION

■ 1.8GHz min. count frequency

The SY10/100E137 are very high speed binary ripple

counters. The two least significant bits were designed

with very fast edge rates, while the more significant bits

maintain standard ECLinPS output edge rates. This allows

the counters to operate at very high frequencies, while

maintaining a moderate power dissipation level.

■ Extended 100E VEE range of –4.2V to –5.5V

■ Synchronous and asynchronous enable pins

■ Differential clock input and data output pins

■ VBB output for single-ended use

The devices are ideally suited for multiple frequency

clock generation, as well as for counters in high-

performance ATE time measurement boards.

■ Asynchronous Master Reset

■ Internal 75KΩ input pull-down resistors

■ Available in 28-pin PLCC packge

Both asynchronous and synchronous enables are

available to maximize the device's flexibility for various

applications. The asynchronous enable input, A_Start,

when asserted, enables the counter while overriding any

synchronous enable signals. The E137 features XOR'ed

enable inputs, EN1 and EN2, which are synchronous to

the CLK input. When only one synchronous enable is

asserted, the counter becomes disabled on the next CLK

transition. All outputs remain in the previous state poised

for the other synchronous enable or A_Start to be

asserted in order to re-enable the counter. Asserting

both synchronous enables causes the counter to become

enabled on the next transition of the CLK. EN1 (or EN2)

and CLK edges are coincident. Sufficient delay has been

inserted in the CLK path (to compensate for the XOR

gate delay and the internal D-flip-flop set-up time) to

ensure that the synchronous enable signal is clocked

correctly; hence, the counter is disabled.

PIN NAMES

CLK, CLK

Q0–Q7, Q0–Q7

A_Start

EN1, EN2

Function

Differential Clock Inputs

Differential Q Outputs

Asynchronous Enable Input

Synchronous Enable Inputs

Asynchronous Master Reset

Switching Reference Output

VCC to Output

VBB

VCCO

The E137 can also be driven single-endedly utilizing

the VBB output supply as the voltage reference for the

CLK input signal. If a single-ended signal is to be used,

the VBB pin should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. VBB can

only source/sink 0.5mA; therefore, it should be used as

a switching reference for the E137 only.

All input pins left open will be pulled LOW via an input

pull-down resistor. Therefore, do not leave the differential

CLK inputs open. Doing so causes the current source

transistor of the input clock gate to become saturated,

thus upsetting the internal bias regulators and

jeopardizing the stability of the device.

The asynchronous Master Reset resets the counter to

an all zero state upon assertion.

Rev.: E

Amendment:/0

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5

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