GS8128018/36RT-333M/250M
GS864018/36RT-333M/250M
GS832018/36RT-333M/250M
333 MHz–250 MHz
Rad-Tolerant SRAM
144Mb/72Mb/36Mb PL/FT Synchronous Burst SRAMs
100-Pin TQFP
Military Temp
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Features
• Aerospace-Level Product
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
• Automatic power-down for portable applications
• 100-pin TQFP package
Radiation Performance
• Total Ionizing Dose (TID) > 50krads(Si)
• Destructive Single Event Latchup Immunity >37 MeV.cm2/mg
(100C)
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Functional Description
Applications
Sleep Mode
The GS8128018/36RT, GS864018/36RT, and
GS832018/36RT are high performance synchronous SRAMs
with a 2-bit burst address counter. Although of a type
originally developed for Level 2 Cache applications supporting
high performance CPUs, these devices now find application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8128018/36RT, GS864018/36RT, and
GS832018/36RT operate on a 2.5 V or 3.3 V power supply. All
inputs are 3.3 V and 2.5 V compatible. Separate output power
Controls
(V
) pins are used to decouple output noise from the
Addresses, data I/Os, chip enables (E1 and E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
DDQ
internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-333M -250M
Unit
tKQ
2.5
3.0
2.5
4.0
ns
ns
tCycle
Pipeline
3-1-1-1
Curr (x18)
Curr (x36)
530
600
430
470
mA
mA
tKQ
tCycle
4.5
4.5
5.5
5.5
ns
ns
Flow Through
2-1-1-1
Curr (x18)
Curr (x36)
400
435
360
380
mA
mA
Rev: 1.01a 10/2020
1/25
© 2018, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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