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SY87700LZG PDF预览

SY87700LZG

更新时间: 2024-09-25 03:12:35
品牌 Logo 应用领域
麦瑞 - MICREL 电信集成电路光电二极管异步传输模式ATM时钟
页数 文件大小 规格书
14页 569K
描述
3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY

SY87700LZG 数据手册

 浏览型号SY87700LZG的Datasheet PDF文件第2页浏览型号SY87700LZG的Datasheet PDF文件第3页浏览型号SY87700LZG的Datasheet PDF文件第4页浏览型号SY87700LZG的Datasheet PDF文件第5页浏览型号SY87700LZG的Datasheet PDF文件第6页浏览型号SY87700LZG的Datasheet PDF文件第7页 
3.3V 32-175Mbps AnyRate®  
CLOCK AND DATA RECOVERY  
SY87700L  
FEATURES  
DESCRIPTION  
Industrial temperature range (–40°C to +85°C)  
3.3V power supply  
The SY87700L is a complete Clock Recovery and Data  
Retiming integrated circuit for data rates from 32Mbps  
up to 175Mbps NRZ. The device is ideally suited for  
SONET/SDH/ATM applications and other high-speed data  
transmission systems.  
Clock recovery and data retiming is performed by  
synchronizing the on-chip VCO directly to the incoming  
data stream. The VCO center frequency is controlled by  
the reference clock frequency and the selected divide  
ratio. On-chip clock generation is performed through the  
use of a frequency multiplier PLL with a byte rate source  
as reference.  
SONET/SDH/ATM compatible  
Clock and data recovery from 32Mbps up to  
175Mbps NRZ data stream, clock generation from  
32Mbps to 175Mbps  
Two on-chip PLLs: one for clock generation and  
another for clock recovery  
Selectable reference frequencies  
Differential PECL high-speed serial I/O  
Line receiver input: no external buffering needed  
Link Fault indication  
The SY87700L also includes a link fault detection  
circuit.  
All support documentation can be found on Micrel’s web  
site at: www.micrel.com.  
100k ECL compatible I/O  
Complies with Bellcore, ITU/CCITT and ANSI  
specifications for applications such as OC-1 and  
OC-3 as well as proprietary applications  
APPLICATIONS  
Available in 32-pin EPAD-TQFP and 28-pin SOIC  
packages (28-pin SOIC is available, but is not  
recommended for new designs.)  
SONET/SDH/ATM OC-1 and OC-3  
Fast Ethernet, SMPTE 259  
Proprietary architecture up to 175Mbps  
BLOCK DIAGRAM  
PLLR P/N  
RDOUTP  
(PECL)  
RDINP  
(PECL)  
RDINN  
PHASE  
DETECTOR  
RDOUTN  
RCLKP  
(PECL)  
0
1
CHARGE  
PUMP  
VCO  
RCLKN  
PHASE/  
FREQUENCY  
DETECTOR  
LINK  
FAULT  
DETECTOR  
CD  
LFIN  
(TTL)  
(PECL)  
REFCLK  
(TTL)  
PHASE/  
FREQUENCY  
DETECTOR  
CHARGE  
PUMP  
VCO  
TCLKP  
(PECL)  
1
0
TCLKN  
VCC  
DIVIDER  
VCCA  
BY 8, 10, 16, 20  
VCCO  
SY87700L  
GND  
DIVSEL 1/2  
PLLS P/N  
(TTL)  
FREQSEL 1/2/3  
(TTL)  
CLKSEL  
(TTL)  
AnyRate is a registered trademark of Micrel, Inc.  
Rev.: H  
Amendment: /0  
M9999-111406  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: September2006  

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