SY10E167JCTR

更新时间： 2024-01-10 10:10:12

品牌	Logo	应用领域
麦瑞 - MICREL		触发器逻辑集成电路
页数	文件大小	规格书
3页	158K
描述
6-BIT 2:1 MUX-REGISTER

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中文翻译

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数据手册

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SY10E167JCTR 数据手册

SY10E167

SY100E167

SY10E167

SY100E167

6-BIT 2:1 MUX-REGISTER

SYNERGY

SEMICONDUCTOR

FEATURES

DESCRIPTION

■ 1000MHz min. operating frequency

■ Extended 100E VEE range of –4.2V to –5.5V

■ 800ps max. clock to output

■ Single-ended outputs

The SY10/100E167 offer six 2:1 multiplexers followed

by D flip-flops with single-ended outputs, designed for use

in new, high-performance ECL systems. The Select (SEL)

control allows one of the two data inputs to the multiplexer

to pass through. The two external clock signals (CLK1,

CLK2) are gated through a logical OR operation before use

as control for the six flip-flops. The selected data are

transferred to the flip-flops on the rising edge of CLK1 or

CLK2 (or both).

■ Asynchronous Master Reset

■ Dual clocks

■ Fully compatible with industry standard 10KH,

100K ECL levels

The multiplexer operation is controlled by the Select

(SEL) signal which selects one of the two bits of input data

at each mux to be passed through.

■ Internal 75KΩ input pulldown resistors

■ ESD protection of 2000V

When a logic HIGH is applied to the Master Reset (MR)

signal, it operates asychronously to take all outputs Q to a

logic LOW.

■ Fully compatible with Motorola MC10E/100E167

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN CONFIGURATION

D0a

MUX

SEL

D0b

D1a

25 24 23 22 21 20 19

MUX

SEL

CLK

VCC

D1b

D2a

TOP VIEW

PLCC

VEE

J28-1

MUX

SEL

VCCO

D2b

D3a

10 11

MUX

SEL

D3b

D4a

MUX

SEL

PIN NAMES

D4b

D5a

D0a–D5a

D0b–D5b

SEL

Function

Input Data a

Input Data b

Select Input

Clock Inputs

Master Reset

Data Outputs

VCC to Output

MUX

SEL

D5b

SEL

CLK1, CLK2

CLK1

CLK2

Q0–Q5

VCCO

Rev.: C

Amendment: /1

Issue Date: February, 1998

5-127

12 3

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