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SY100EPT21LKC PDF预览

SY100EPT21LKC

更新时间: 2024-09-29 22:10:03
品牌 Logo 应用领域
麦瑞 - MICREL 锁存器接口集成电路光电二极管
页数 文件大小 规格书
8页 89K
描述
3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR

SY100EPT21LKC 数据手册

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3.3V DIFFERENTIAL  
LVPECL-to-LVTTL  
TRANSLATOR  
SY100EPT21L  
DESCRIPTION  
FEATURES  
3.3V power supply  
The SY100EPT21L is a single differential LVPECL-to-  
LVTTL translator using a single +3.3V power supply.  
Because LVPECL (Low Voltage Positive ECL) levels are  
used, only +3.3V and ground are required. The small  
outline 8-lead SOIC package and low skew single gate  
design make the EPT21L ideal for applications that  
require the translation of a clock or data signal where  
minimal space, low power, and low cost are critical.  
1.9ns typical propagation delay  
275MHz f  
(Clock bit stream, not pseudo-random)  
MAX  
Differential LVPECL inputs  
24mA LVTTL outputs  
Flow-through pinouts  
Internal input resistors: pulldown on D, pulldown  
V
allows a differential, single-ended, or AC-coupled  
BB  
and pullup on /D  
interface to the device. If used, the V output should be  
BB  
Q output will default LOW with inputs open or at  
bypassed to V  
with 0.01µF capacitor.  
CC  
GND  
Under open input conditions, the /D will be biased at a  
V /2 voltage level and the D input will be pulled to  
CC  
V output  
BB  
ground. This condition will force the Q output low to  
provide added stability.  
Available in 8-pin MSOP and SOIC package  
The 100EPT is compatible with positive ECL 100K  
logic levels.  
PIN NAMES  
PIN CONFIGURATION/BLOCK DIAGRAM  
Pin  
Function  
LVTTL Output  
Q
NC  
D
1
2
3
4
8
7
6
5
VCC  
Q
LVTTL  
D, /D  
VCC  
Differential LVPECL Input Pair  
Positive Supply  
LVPECL  
D
NC  
GND  
VBB  
Output Reference Voltage  
Ground  
VBB  
GND  
(Available in 8-pin SOIC and 8-pin MSOP)  
Rev.: A  
Amendment:/1  
1
Issue Date: July 2000  

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