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STM6503REAADG6F

更新时间: 2024-01-08 15:34:45
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意法半导体 - STMICROELECTRONICS /
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29页 450K
描述
Dual push-button Smart ResetTM with user-adjustable setup delays

STM6503REAADG6F 技术参数

生命周期:ActiveReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:10 weeks风险等级:5.6
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUIT峰值回流温度(摄氏度):NOT SPECIFIED
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

STM6503REAADG6F 数据手册

 浏览型号STM6503REAADG6F的Datasheet PDF文件第4页浏览型号STM6503REAADG6F的Datasheet PDF文件第5页浏览型号STM6503REAADG6F的Datasheet PDF文件第6页浏览型号STM6503REAADG6F的Datasheet PDF文件第8页浏览型号STM6503REAADG6F的Datasheet PDF文件第9页浏览型号STM6503REAADG6F的Datasheet PDF文件第10页 
STM6502, STM6503, STM6504, STM6505  
Description  
Table 2.  
Symbol  
Signal names  
Input/  
Description  
output  
RST  
BLD  
Output Open-drain reset output, active-low.  
Output Battery low detect output, active-low, open-drain. STM6505 only.  
Primary push-button Smart Reset input. Active-low, with or without internal  
SR0  
SR1  
Input  
Input  
65 kΩ pull-up to V (product options).  
CC  
Secondary push-button Smart Reset input - combines with the primary push-  
button reset to provide setup delay time before reset. Active-low, with or without  
internal 65 kΩ pull-up to V (product options).  
CC  
Secondary push-button Smart Reset input - provides instant Smart Reset. SRE  
is edge-triggered with a special debounce time (t  
the falling edge after a valid reset period. Active-high, no internal pull-up to V  
STM6504 only.  
= 240 ms min.) at  
DEBOUNCE  
SRE  
SRC  
Input  
Input  
.
CC  
Smart Reset input delay setup control: connect to an external capacitor to adjust  
the delay setup time (t ). STM6502 and STM6505 only.  
SRC  
A three-state Smart Reset input delay setup control. When connected to  
ground, t = 2 s; when left open, t = 6 s; when connected to V  
,
CC  
SRC  
SRC  
t
= 10 s (all times are minimum). TSR is a DC-type input, intended to be  
SRC  
TSR  
Input  
either permanently grounded, permanently connected to V or permanently  
CC  
left open. If left open, for improved system glitch immunity it is strongly  
recommended to connect a 0.1 µF decoupling ceramic capacitor between the  
TSR and V pins. STM6503 and STM6504 only.  
SS  
Supply voltage input. Power supply for the device and an input for the monitored  
V
Supply supply voltage. A 0.1 µF decoupling ceramic capacitor is recommended to be  
connected between the V and V pins.  
CC  
CC  
SS  
V
Input  
Supply Ground  
No connect (not bonded); should be connected to V  
Battery voltage monitoring input. STM6505 only.  
BAT  
V
SS  
NC  
.
SS  
Doc ID 16101 Rev 5  
7/29  

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