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STM32F407VEH7XXX PDF预览

STM32F407VEH7XXX

更新时间: 2024-01-21 17:32:22
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 外围集成电路
页数 文件大小 规格书
167页 2187K
描述
RISC MICROCONTROLLER

STM32F407VEH7XXX 技术参数

生命周期:Active包装说明:BGA,
Reach Compliance Code:compliant风险等级:5.67
位大小:32端子数量:100
封装代码:BGA表面贴装:YES
技术:CMOSuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC

STM32F407VEH7XXX 数据手册

 浏览型号STM32F407VEH7XXX的Datasheet PDF文件第4页浏览型号STM32F407VEH7XXX的Datasheet PDF文件第5页浏览型号STM32F407VEH7XXX的Datasheet PDF文件第6页浏览型号STM32F407VEH7XXX的Datasheet PDF文件第8页浏览型号STM32F407VEH7XXX的Datasheet PDF文件第9页浏览型号STM32F407VEH7XXX的Datasheet PDF文件第10页 
STM32F405xx, STM32F407xx  
List of figures  
List of figures  
Figure 1.  
Figure 2.  
Compatible board design between STM32F10xx/STM32F4xx for LQFP64. . . . . . . . . . . . 14  
Compatible board design STM32F10xx/STM32F2xx/STM32F4xx  
for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx  
for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Compatible board design between STM32F2xx and STM32F4xx  
Figure 3.  
Figure 4.  
for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
STM32F40x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Regulator ON/internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Startup in regulator OFF: slow V slope  
DD  
- power-down reset risen after V  
/V  
stabilization . . . . . . . . . . . . . . . . . . . . . . . . 26  
CAP_1 CAP_2  
Figure 9.  
Startup in regulator OFF mode: fast V slope  
DD  
- power-down reset risen before V  
/V  
stabilization . . . . . . . . . . . . . . . . . . . . . . 26  
CAP_1 CAP_2  
Figure 10. STM32F40x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Figure 11. STM32F40x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Figure 12. STM32F40x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Figure 13. STM32F40x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Figure 14. STM32F40x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Figure 15. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
Figure 16. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
Figure 17. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
Figure 18. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Figure 19. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64  
Figure 20. External capacitor C  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68  
EXT  
Figure 21. Typical current consumption vs temperature, Run mode, code with data  
processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 73  
Figure 22. Typical current consumption vs temperature, Run mode, code with data  
processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 73  
Figure 23. Typical current consumption vs temperature, Run mode, code with data  
processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 74  
Figure 24. Typical current consumption vs temperature, Run mode, code with data  
processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 74  
Figure 25. Typical V  
Figure 26. Typical V  
current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 77  
current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 78  
BAT  
BAT  
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85  
Figure 28. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85  
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86  
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
Figure 31. ACC versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
LSI  
Figure 32. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93  
Figure 33. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93  
Figure 34. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102  
Figure 35. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103  
2
Figure 36. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107  
Figure 37. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109  
(1)  
Figure 38. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109  
(1)  
Figure 39. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110  
Doc ID 022152 Rev 2  
7/167  

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