SS8219G
Ultra320 Multi-mode LVD/SE SCSI Terminator
PRODUCT SUMMARY
DESCRIPTION
The SS8219G multi-mode LVD/SE SCSI terminator
provides a smooth transition between modes of the
SCSI Parallel Interface. It automatically senses the bus
via DIFFSENS and switches the termination to either
single-ended (SE) or low voltage differential (LVD) SCSI,
based on which type of devices are connected to the bus.
If the SS8219G detects an HVD SCSI device, it switches
to a high impedance state.
SPI mode auto-detection/switching.
Pin/pin compatible with popular industry
standard parts DS2118/9 and UCC5672
FEATURES
Auto-selectable single-ended or LVD termination
Meets SCSI-1, SCSI-2, SCSI-3 SPI Ultra (Fast-20),
Ultra 2 (SPI-2 LVD), Ultra160 (SPI-3 LVD)
and Ultra320 (SPI-4 LVD) standards
Supports active negation
Channel capacitance of 3pF
Operation from 2.9V to 5.5V
Thermal protection
Hot-swap compatible
Tolerance of 5% on termination resistance
Available in 28 pin TSSOP or 36 pin SSOP
A 16-bit wide SCSI bus requires three SS8219G for
termination.
This multi-mode terminator contains all the functions
to terminate, auto detect and switch modes for SCSI
Parallel Interface (SPI) bus architectures.
For SE termination, one regulator and nine precision 110W
resistors are used.
For LVD termination, the SS8219G integrates 18 regulated
supplies with nine precision resistor strings.
Pb-free, RoHS compliant.
APPLICATIONS
High performance data storage systems in servers,
workstations, high-end and industrial PCs, and RAID
disk arrays.
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
TPWR
HVD
VREF
NC
LVD
NC
R1+
R1-
SE
28
27
26
25
24
23
22
1
2
TPWR
VREF
R1+
R1-
R9-
R9+
R8-
TPWR
R9-
R2+
R2-
3
4
R9+
R2+
R2-
HS/GND
HS/GND
8
9
R8+
HS/GND
5
R8-
R8+
NC/ HS GND
R3+
6
10
11
12
HS/GND
HS/GND
R3+
NC/ HS GND
7
26 HS/GND
R3-
21 R7-
8
25
R3-
R7-
R4+
20
9
R7+
24
23
22
R4+ 13
R7+
R4-
R5+
19 R6-
10
11
12
14
R4-
R6-
R6+
18
17
15
16
17
R5+
R5-
R6+
DIFFB
R5-
21 DIFFB
13
14
16 DIFFSENSE
15 M/S
DISCNCT
20
19
DIFFSENSE
M/S
DISCNCT
GND
GND
18
28 pin TSSOP
36 pin SSOP
12/06/2005 Rev.3.01
www.SiliconStandard.com
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