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SR5E1E3 PDF预览

SR5E1E3

更新时间: 2024-10-02 14:57:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
6页 155K
描述
SR5 E1 line of Stellar electrification MCUs, 32-bit Arm Cortex M7 automotive MCU 2x cores, 2 MB Flash, rich analog, high-resolution timer, HSM, ASIL-D

SR5E1E3 数据手册

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SR5E1x  
Data brief  
SR5 E1 line of Stellar electrification MCUs — 32-bit Arm® Cortex®M7 automotive  
MCU 2x cores, 2 MB Flash, rich analog, high-resolution timer, HSM, ASIL-D  
Features  
AEC-Q100 automotive qualification on going  
SR5 high-performance analog MCUs offering:  
Digital and analog high-frequency control requested by new wide-bandgap  
technologies (Silicon Carbide and Gallium Nitride)  
eTQFP100 (14 x 14 x 1.0 mm)  
Superior real-time and functional safety performance (ASIL-D capability)  
Built-in fast and cost optimized OTA (over-the-air) reprogramming capability  
(with built-in dual image storage)  
High-speed security cryptographic services (HSM)  
Cores  
2x 32-bit Arm® Cortex®M7 with double-precision FPU, L1 cache and DSP  
eLQFP176 (24 x 24 x 1.4 mm)  
instructions  
Split-lock configuration, allowing either 2 cores in parallel or 1 core in  
lockstep configuration  
2 DMA engines in lockstep configuration  
Memories  
Up to 2 MB on-chip Flash memory with read while write support  
1920 KB code Flash memory split in two banks allowing 960 KB OTA  
reprogramming support  
Part number  
SR5E1E3  
Package  
160 KB HSM dedicated code Flash memory  
eTQFP100  
eLQFP176  
96 KB data Flash memory (64 KB + 32 KB dedicated to HSM)  
488 KB on-chip general-purpose SRAM:  
SR5E1E7  
2x 32 KB instruction TCM + 2x 64 KB data TCM  
256 KB system RAM  
40 KB HSM dedicated system RAM  
Security: hardware security module (HSM)  
On-chip high-performance security module with dedicated RAM and Flash  
Based on Cortex®M0+ core  
Hardware accelerator for symmetric cryptography  
Safety: comprehensive new generation ASIL-D safety concept  
State of the art safety measures at all level of the architecture for most efficient  
implementation of ISO26262 ASIL-D functionalities  
FCCU for collection and reaction to failure notifications with enhanced  
configurability  
Memory error management unit (MEMU) for collection and reporting of error  
events in memories  
Cyclic redundancy check (CRC) unit  
DB4448 - Rev 2 - January 2022  
For further information contact your local STMicroelectronics sales office.  
www.st.com  

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