Datasheet > SPXD2010VMM120R

SPXD2010VMM120R

更新时间： 2022-02-26 10:40:14

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
30页	137K
描述
32-bit Power ArchitectureÂ® Microcontrollers for Highly Reliable

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数据手册

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SPXD2010VMM120R 数据手册

Features

— Selectable pull-up, pull-down or no pull on all pins on all SIU controlled pins

— Selectable open drain

•

Redundant temperature sensors in separate safety channels

Multiple low/high voltage detector and inhibit units

— High voltage detection and inhibit with off-line testing capability on 1.2 V only

— Low voltage detection and inhibit with off-line testing capability on 1.2 V and 3.3 V supply

Redundant bandgap to duplicate internal reference

•

Deep N-well and wide column multiplexing where required to reduce Soft error rate (SER) effect

for SRAM

•

Physical separation of replicated functional blocks achieved by layout

2.4

Modes of Operation

PXS20 devices can operate in two modes of operation:

•

Lock Step Mode (LSM)

Decoupled Parallel Mode (DPM)

One of the two modes is statically selected at power-up. The selected mode may be changed only going

through a full power-on reset.

2.4.1

Lock Step Mode (LSM)

Lock Step Mode (LSM) allows reaching the highest safety level. It has been defined to allow reaching

SIL3 with minimum software overhead.

The Sphere of Replication (SoR) refers to a set of replicated IP modules where at the outputs a formal

check is performed to ensure that the same operations or transactions are executed on a clock per clock

basis (Lock Step Mode of operation).

The current concept assumes as premise that the most important goal for a functional safety SIL3-capable

device is to detect (or diagnose) faults as they leave the SoR. In fact, a fault as long as it remains confined

within the SoR and therefore will not generate an action visible outside the SoC or influence the effective

operability of the periphery (and so the ECU), is not to be considered as a dangerous fault.

The presence of checkers (RC) at the outputs of the SoR for the periphery bus, the flash-memory

subsystem and the SRAM subsystem represents a minimum guarantee that non-common cause faults are

detected when the two channels redundantly are merged into a single actuator or recipient, on the action

that is to be performed.

2.4.2

Decoupled Parallel Mode (DPM)

In Decoupled Parallel Mode (DPM) , each CPU core and connected channel run independently from the

other one and redundancy checkers (RC) are disabled.

PXS20 Product Brief, Rev. 1

Freescale Semiconductor

1...4 5 678 9 10...30

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