Datasheet > SPXD2010VMM120R

SPXD2010VMM120R

更新时间： 2022-02-26 10:40:14

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
30页	137K
描述
32-bit Power ArchitectureÂ® Microcontrollers for Highly Reliable

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SPXD2010VMM120R 数据手册

Application Examples

system. In order to minimize software overhead and improve operational reliability, all major systems such

as CPU core, DMA controller, interrupt controller, crossbar bus system, memory systems, peripheral

systems, and memory protection unit, include built in redundancy and or robust system monitoring. Lock

Step Redundancy Checking Units are implemented at each output of this Sphere of Replication (SoR).

ECC is available for on-chip RAM and flash memories. A programmable fault collection and control unit

monitors the integrity status of the device and provides flexible safe state control.

The host processor core of the PXS20 is the latest CPU from the e200 family of compatible Power

Architecture cores. The e200z4d 5-stage pipeline dual issue core provides a very high level of efficiency,

allowing high performance with minimum power consumption.

The peripheral set provides high-end electrical motor control capability with very low CPU intervention,

thanks to the on-chip Cross Triggering Unit (CTU).

This device incorporates high-performance 90 nm embedded flash-memory technology to provide sub-

stantial cost reduction per feature and significant performance improvement.

Application Examples

The PXS20 can be used for a variety of safety applications such as:

•

Safety shutdown systems

Solar inverters

Motor drives

Factory automation

Aerospace

Robotics

Features

This section describes the features of the PXS20 family.

PXS20 Product Brief, Rev. 1

Freescale Semiconductor

123 4 5 6 7...30

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