Datasheet > SPFMPR302

SPFMPR302

更新时间： 2024-02-04 11:57:46

品牌	Logo	应用领域
安华高科 - AVAGO		放大器光纤
页数	文件大小	规格书
7页	647K
描述
FIBER OPTIC RECEIVER, 25Mbps, THROUGH HOLE MOUNT, CAI PACKAGE-4

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SPFMPR302 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	风险等级：	5.57
主体宽度：	3.4 mm	主体高度：	6.2 mm
主体长度或直径：	9.6 mm	内置特性：	AMPLIFIER
数据速率：	25 Mbps	发射极/检测器类型：	PIN PHOTODIODE
光纤设备类型：	RECEIVER	光纤类型：	POF
安装特点：	THROUGH HOLE MOUNT	最高工作温度：	85 °C
最低工作温度：	-40 °C	标称工作波长：	850 nm
接收类型：	DIGITAL	灵敏度：	-24.5 dBm
子类别：	Fiber Optic Receivers	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	NO	Base Number Matches：	1

SPFMPR302 数据手册

Design & Layout rules

• The 100nF bypass capacitors of the FOTs must be located as close as possible between the pins V and GND of the

FOTs. Use ceramic caps and tantalum caps with low ESR.

• Also the inductor/ ferrite bead (receiver) and the -3dB - control circuit (transmitter) must be placed as close as

possible to the FOTs. We prefer ferrite beads (e.g. type 74279214 Würth Elektronik) since the D.C. resistance is very

low. In case other inductors are used, the D.C. resistance should be less than 3Ohm.

• For EMC, a ferrite bead should be connected to the power supply, close to the transmitter and the receiver. Do not

use only one ferrite bead together for receiver and transmitter!

• For the ground connection a ground plane is recommended (Y-structure). That means the ground planes of the

transmitter, the receiver and the shielding must be separated. The three ground planes should be connected

together behind the bypass capacitors (refer to the PCB design below). This ground signal should be connected

directly to the ground plane of the MOST controller (e.g. OS8104) and the power supply on the top layer and/or

bottom layer and ground layer as it is indicated in the example below.

• If a multi layer design is used the ground layer must have the same ground separation like shown for the top layer!

• A serial resistor in the Rx/ Tx data line will also reduce EMC - problems. For Rx the resistor must be placed near the

receiver - for Tx the resistor must be placed near the MOST controller chip. The value depends on the distance

between the FOTs and the MOST chip (< 5cm) and can be within a range up to 150R. Higher values for the resistors

will increase jitter and can therefore cause locking problems of the MOST PLL!

• The Rx/ Tx signals should not be routed in parallel over a long distance, but may be embedded with ground copper,

if possible.

• The GND pin and the pin of R (15K - resistor) of the transmitter are used for heat dissipation. Therefore there

ext

should be a good connection to the PCB - no isolation gaps! Both pins should dip into a copper area (see layout

example below).

Layout example

The reference board from OASIS Silicon Systems follows the requirements above. The schematic is very similar to the

example above, but does not include the connection to the power supply, the OS8104 or the micro controller.

The examples below for top- and bottom layer is the layout of the reference design board and shows how the layout

around the optical receiver and transmitter should look like.

It is strongly recommended to follow these examples in your design to get best performance!

Note:

1. The buﬀer circuit (IC1), the connectors and jumpers in the middle to the right section of the schematic are only for being used together with the

reference board, and will not be necessary for your hardware design.

1 2 3 456 7

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