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SPEAR1310

更新时间: 2024-01-13 19:24:24
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意法半导体 - STMICROELECTRONICS 通信
页数 文件大小 规格书
57页 811K
描述
Dual-core Cortex A9 embedded MPU for communications

SPEAR1310 数据手册

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SPEAr1310  
Dual-core Cortex A9 embedded MPU for communications  
Data brief  
Features  
CPU subsystem:  
– 2x ARM Cortex A9 cores, up to 600 MHz  
– Supporting both symmetric (SMP) and  
asymmetric (AMP) multiprocessing  
PBGA (23 x 23 mm)  
– 2x I2S ports for external audio/modem  
– 6x UARTs (up to 5 Mbaud)  
32+32 KB L1 Instructions/Data cache per  
core with parity check  
– Shared 512 KB L2 cache (ECC protected)  
with parity check  
– 1x SSP port (SPI and other protocols),  
master/slave, up to 41 Mbps  
– Accelerator coherence port (ACP)  
– 2x I2C ports master/slave  
Bus: 64-bit multilayer network-on-chip  
Integrated support for external peripherals:  
– TFT LCD controller, up to 1920 x 1200 (60  
Hz), 24 bpp  
Memories:  
– 32 KB BootROM  
– 32 KB internal SRAM  
– Multi-port controller (MPMC) for external  
DDR2-800/DDR3-1066 with 16/32 bits  
datapath, up to 1GB addressable with ECC  
option for SEC/DED  
Touchscreen I/F (4-wire resistive)  
– 9 x 9 keyboard controller  
– Memory card interface (MCIF) supporting  
SD/SDIO 2.0, SDHC, MMC 4.2/4.3,  
CF/CF+ Rev 4.1, XD  
– Controller (FSMC) for external NAND  
Flash, parallel NOR Flash and  
asynchronous SRAM  
Expansion interface (EXPI)  
Security: C3 cryptographic accelerator  
13x timers and 1x real time clock  
Miscellaneous functions:  
– Controller (SMI) for external serial NOR  
flash  
– 2x high-performance 8-channels DMA  
controllers  
Connectivity:  
– 2x Giga/Fast Ethernet ports (for external  
GMII/RGMII/MII PHY)  
– JPEG HW codec  
– 10 bit ADC, up to 1 Msps, 8 inputs with  
autoscan capability  
– 3x Fast Ethernet (for external SMII/RMII  
PHY)  
– Programmable bidirectional GPIO signals  
with interrupt capability  
– 3x PCIe 2.0 links (embedded PHY)  
– 3x SATA gen-2 host port  
– 1x 32-bit PCI expansion bus (up to 66 MHz)  
– 2x USB 2.0 host ports with integrated  
PHYs  
– 510 + 209 one time programmable (OTP)  
bits  
– Embedded sensor for junction temperature  
monitoring  
– 1x USB2.0 OTG port with integrated PHY  
– 2x CAN 2.0 a/b interfaces  
– 2x TDM/E1 HDLC controllers with 256/32  
time slots per frame respectively  
– JTAG-PTM (debugging and test interface)  
Power saving features:  
– Power islands for leakage reduction  
– IP clock gating for dynamic power reduction  
– Dynamic frequency scaling  
– 2x HDLC controllers for external RS485  
PHYs  
September 2010  
Doc ID 17528 Rev 4  
1/57  
For further information contact your local STMicroelectronics sales office.  
www.st.com  
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